Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
| dc.citation.epage | 642 | en_US |
| dc.citation.issue | 9 | en_US |
| dc.citation.spage | 640 | en_US |
| dc.citation.volume | 25 | en_US |
| dc.citation.woscount | 17 | |
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.author | Lin, KH | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:38:37Z | |
| dc.date.available | 2014-12-08T15:38:37Z | |
| dc.date.issued | 2004-09-01 | en_US |
| dc.description.abstract | The double snapback characteristic in the highvoltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit. | en_US |
| dc.identifier.doi | 10.1109/LED.2004.833372 | en_US |
| dc.identifier.issn | 0741-3106 | en_US |
| dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/LED.2004.833372 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/26417 | |
| dc.identifier.wosnumber | WOS:000223577600017 | |
| dc.language.iso | en_US | en_US |
| dc.subject | double-diffused drain (DDD) | en_US |
| dc.subject | electrostatic discharge (ESD) | en_US |
| dc.subject | high-voltage nMOSFET | en_US |
| dc.subject | lateral diffused MOS (LDMOS) | en_US |
| dc.subject | latchup | en_US |
| dc.title | Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design | en_US |
| dc.type | Article | en_US |