Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

dc.citation.epage	216	en_US
dc.citation.spage	213	en_US
dc.contributor.author	Chang, WJ	en_US
dc.contributor.author	Ker, MD	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:25:51Z
dc.date.available	2014-12-08T15:25:51Z
dc.date.issued	2004	en_US
dc.description.abstract	Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-mum and 0.25-mum CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-mum salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.	en_US
dc.identifier.isbn	0-7803-8454-7	en_US
dc.identifier.journal	IPFA 2004: PROCEEDINGS OF THE 11TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18278
dc.identifier.wosnumber	WOS:000224428800053
dc.language.iso	en_US	en_US
dc.title	Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces	en_US
dc.type	Proceedings Paper	en_US

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