Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Abstract

Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-mum and 0.25-mum CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-mum salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.