Computation-effective 3-D graphics rendering architecture for embedded multimedia system
| dc.citation.epage | 743 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 735 | en_US |
| dc.citation.volume | 46 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Liang, BS | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:44:56Z | |
| dc.date.available | 2014-12-08T15:44:56Z | |
| dc.date.issued | 2000-08-01 | en_US |
| dc.description.abstract | A new architecture is proposed to realize 3-D graphics rendering for embedded multimedia system. Because only 20% to 83% triangles in original 3-D object models are visible by simulation, our architecture is designed to eliminate the redundant operations on invisible triangles without image quality loss. It bases on our index rendering and enhanced deferred lighting approaches, and its feature is dual pipeline rendering architecture. The simulation and analysis results show that this architecture can save up to 63.4% CPU operations compared with traditional architectures. | en_US |
| dc.identifier.doi | 10.1109/30.883440 | en_US |
| dc.identifier.issn | 0098-3063 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/30.883440 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/30343 | |
| dc.identifier.wosnumber | WOS:000089667900044 | |
| dc.language.iso | en_US | en_US |
| dc.title | Computation-effective 3-D graphics rendering architecture for embedded multimedia system | en_US |
| dc.type | Article | en_US |