Sensitisable-path-oriented clustered voltage scaling technique for low power
| dc.citation.epage | 307 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 301 | en_US |
| dc.citation.volume | 145 | en_US |
| dc.citation.woscount | 3 | |
| dc.contributor.author | Jou, JY | en_US |
| dc.contributor.author | Chou, DS | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:48:55Z | |
| dc.date.available | 2014-12-08T15:48:55Z | |
| dc.date.issued | 1998-07-01 | en_US |
| dc.description.abstract | Because the average power consumption of CMOS digital circuits is consumption proportional voltage, a clustered voltage scaling (CVS) technique has previously been proposed to reduce power without sacrificing the circuit performance. In this paper the authors propose a path-oriented CVS algorithm, which can take the false paths into account. Extensive experiments are conducted on ISCAS85 benchmark circuits. These experiments show that many more gates can be voltage scaled down in comparison with the original CVS technique. An additional 22% power reduction ratio over that of the original CVS technique is achieved. | en_US |
| dc.identifier.issn | 1350-2387 | en_US |
| dc.identifier.journal | IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/32538 | |
| dc.identifier.wosnumber | WOS:000075323100008 | |
| dc.language.iso | en_US | en_US |
| dc.subject | clustered voltage scaling technique | en_US |
| dc.subject | benchmark circuits | en_US |
| dc.title | Sensitisable-path-oriented clustered voltage scaling technique for low power | en_US |
| dc.type | Article | en_US |