A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
| dc.citation.epage | 1355 | en_US |
| dc.citation.issue | 10 | en_US |
| dc.citation.spage | 1351 | en_US |
| dc.citation.volume | E96C | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Wang, Li-Rong | en_US |
| dc.contributor.author | Lo, Kai-Yu | en_US |
| dc.contributor.author | Jou, Shyh-Jye | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:33:44Z | |
| dc.date.available | 2014-12-08T15:33:44Z | |
| dc.date.issued | 2013-10-01 | en_US |
| dc.description.abstract | This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V-t and 0.84 V V-DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V-t technology, as compared to that of the classic double-edge-triggered flip-flop design. | en_US |
| dc.identifier.doi | 10.1587/transele.E96.C.1351 | en_US |
| dc.identifier.issn | 0916-8524 | en_US |
| dc.identifier.journal | IEICE TRANSACTIONS ON ELECTRONICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1587/transele.E96.C.1351 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/23317 | |
| dc.identifier.wosnumber | WOS:000326667800020 | |
| dc.language.iso | en_US | en_US |
| dc.subject | double-edge-triggered | en_US |
| dc.subject | flip-flop | en_US |
| dc.subject | level-converting | en_US |
| dc.subject | sense amplifier | en_US |
| dc.subject | mixed threshold voltage | en_US |
| dc.title | A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design | en_US |
| dc.type | Article | en_US |