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New curvature-compensation technique for CMOS bandgap reference with sub-1-v operation

dc.citation.epage3864en_US
dc.citation.spage3861en_US
dc.contributor.authorKer, MDen_US
dc.contributor.authorChen, JSen_US
dc.contributor.authorChu, CYen_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.date.accessioned2014-12-08T15:25:24Z
dc.date.available2014-12-08T15:25:24Z
dc.date.issued2005en_US
dc.description.abstractA new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic NPN and PNP BJT devices in CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-mu m CMOS process. The experimental results have verified that, at the minimum supply voltage of 0.9 V, the output reference voltage is 536.7 mV with a temperature coefficient of 19.55 ppm/degrees C from 0 degrees C to 100 degrees C. With 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz.en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/17783
dc.identifier.wosnumberWOS:000232002403211
dc.language.isoen_USen_US
dc.titleNew curvature-compensation technique for CMOS bandgap reference with sub-1-v operationen_US
dc.typeProceedings Paperen_US

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