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Architecture design of full HD JPEG XR encoder for digital photography applications

dc.citation.epage971en_US
dc.citation.issue3en_US
dc.citation.spage963en_US
dc.citation.volume54en_US
dc.citation.woscount6
dc.contributor.authorPan, Chia-Hoen_US
dc.contributor.authorChien, Ching-Yenen_US
dc.contributor.authorChao, Wei-Minen_US
dc.contributor.authorHuang, Sheng-Chiehen_US
dc.contributor.authorChen, Liang-Geeen_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.date.accessioned2014-12-08T15:11:05Z
dc.date.available2014-12-08T15:11:05Z
dc.date.issued2008-08-01en_US
dc.description.abstractTo satisfy the high quality image compression requirement, the new, JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 x 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features.en_US
dc.identifier.doi10.1109/TCE.2008.4637574en_US
dc.identifier.issn0098-3063en_US
dc.identifier.journalIEEE TRANSACTIONS ON CONSUMER ELECTRONICSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCE.2008.4637574en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/8498
dc.identifier.wosnumberWOS:000259367300003
dc.language.isoen_USen_US
dc.subjectJPEG XRen_US
dc.subjecthigh definition photoen_US
dc.subjectJoint Photographic Experts Group (JPEG)en_US
dc.subjectVLSI architectureen_US
dc.titleArchitecture design of full HD JPEG XR encoder for digital photography applicationsen_US
dc.typeArticleen_US

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