An efficient and orderly implementation of bypass queue under bursty traffic
| dc.citation.epage | 2148 | en_US |
| dc.citation.issue | 14 | en_US |
| dc.citation.spage | 2143 | en_US |
| dc.citation.volume | 24 | en_US |
| dc.citation.woscount | 2 | |
| dc.contributor.author | Wu, JSC | en_US |
| dc.contributor.author | Lin, YD | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:47:16Z | |
| dc.date.available | 2014-12-08T15:47:16Z | |
| dc.date.issued | 1998-12-01 | en_US |
| dc.description.abstract | Sharma and Pinnu proposed an implementation of bypass queue by many FIFOs; unfortunately, the detailed procedure paid little attention to maintaining cell sequence, which is an important feature in ATM network. In this paper, we propose an improved architecture which guarantees cell sequence integrity and describe its related operating procedures. (C) 1998 Elsevier Science B.V. All rights reserved. | en_US |
| dc.identifier.issn | 0167-8191 | en_US |
| dc.identifier.journal | PARALLEL COMPUTING | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/31717 | |
| dc.identifier.wosnumber | WOS:000077390700011 | |
| dc.language.iso | en_US | en_US |
| dc.subject | bypass queue | en_US |
| dc.subject | cell sequence integrity | en_US |
| dc.subject | head of line blocking | en_US |
| dc.subject | switches | en_US |
| dc.title | An efficient and orderly implementation of bypass queue under bursty traffic | en_US |
| dc.type | Article | en_US |