AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
| dc.citation.epage | 807 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.spage | 802 | en_US |
| dc.citation.volume | 41 | en_US |
| dc.citation.woscount | 19 | |
| dc.contributor.author | SHUNG, CB | en_US |
| dc.contributor.author | LIN, HD | en_US |
| dc.contributor.author | CYPHER, R | en_US |
| dc.contributor.author | SIEGEL, PH | en_US |
| dc.contributor.author | THAPAR, HK | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:04:32Z | |
| dc.date.available | 2014-12-08T15:04:32Z | |
| dc.date.issued | 1993-05-01 | en_US |
| dc.description.abstract | In the previous paper, we established the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm. In this paper, we will show area-efficient architectures for practical codes to illustrate the design procedures and demonstrate the favorable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes will be presented. We will also discuss the application of our area-efficient techniques to codes with a very large numbers of states, codes with time-varying trellises, and a programmable Viterbi decoder. | en_US |
| dc.identifier.doi | 10.1109/26.225495 | en_US |
| dc.identifier.issn | 0090-6778 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON COMMUNICATIONS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/26.225495 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/3022 | |
| dc.identifier.wosnumber | WOS:A1993LR65600020 | |
| dc.language.iso | en_US | en_US |
| dc.title | AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS | en_US |
| dc.type | Article | en_US |