Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
| dc.citation.epage | 321 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 307 | en_US |
| dc.citation.volume | 4 | en_US |
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.author | Wu, CY | en_US |
| dc.contributor.author | Cheng, T | en_US |
| dc.contributor.author | Chang, HH | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:02:23Z | |
| dc.date.available | 2014-12-08T15:02:23Z | |
| dc.date.issued | 1996-09-01 | en_US |
| dc.description.abstract | Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected. | en_US |
| dc.identifier.doi | 10.1109/92.532032 | en_US |
| dc.identifier.issn | 1063-8210 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/92.532032 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/1053 | |
| dc.language.iso | en_US | en_US |
| dc.title | Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC | en_US |
| dc.type | Article | en_US |