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A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTION

dc.citation.epage866en_US
dc.citation.issue9en_US
dc.citation.spage855en_US
dc.citation.volume28en_US
dc.citation.woscount4
dc.contributor.authorCHEN, MJen_US
dc.contributor.authorWU, CYen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.date.accessioned2014-12-08T15:06:15Z
dc.date.available2014-12-08T15:06:15Z
dc.date.issued1985en_US
dc.identifier.issn0038-1101en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/4829
dc.identifier.wosnumberWOS:A1985AQX1400002
dc.language.isoen_USen_US
dc.titleA STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTIONen_US
dc.typeArticleen_US

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