Browsing by Author "CHEN KUAN-NENG"

Now showing 1 - 15 of 15

BONDING METHOD FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT THEREOF
(2013-03-21)
CHEN KUAN-NENG
;
Hsu Sheng-Yao
The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit.
HETEROSTRUCTURE CONTAINING IC AND LED AND METHOD FOR FABRICATING THE SAME
(2012-12-13)
CHEN KUAN-NENG
;
KO CHENG-TA
;
LO WEI-CHUNG
A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.
HETEROSTRUCTURE CONTAINING IC AND LED AND METHOD FOR FABRICATING THE SAME
(2014-01-02)
CHEN KUAN-NENG
;
KO CHENG-TA
;
LO WEI-CHUNG
A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.
三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析( II )
(2011)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析( III )
(2012)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析(I)
(2010)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
本計畫的目的為使用奈米碳管與鎳奈米線材料之矽晶直通孔(TSV)示範三維積體電路測試結構並且建立熱傳導模型、應力分析。本計畫的核心在於將所有相關3D IC製程整合，並至成為一可操作測試的元件結構。首先，矽晶直通孔之製程參數建立包括其準直式蝕刻、蝕刻速率與角度間變異、高深寬比低粗糙度蝕刻等對於後續填孔洞是必須的。再來，設計測試架構平台提供後續製程包括奈米碳管、鎳奈米線之填充，熱模擬分析及應力測試。此測試平台的設計為面對面晶圓銅接合、上層晶圓磨薄、矽晶直通孔(TSV) 蝕刻並且能在實驗室環境下量測。最後，測試結構的電性分析、利用穿透式電子顯微鏡探討側邊架構的填充的品質分析。此外，熱傳在三維積體電路架構下，其熱堆積問題必然會更加嚴重，必須建立其熱傳導模型才可分析不同圖型、材料下矽直通孔去改善熱堆積在三維積體電路的議題。同時，在此之應力分析探討於銅-銅、奈米碳管-催化金屬及接面金屬、鎳-銅接面在不同矽直通孔密度與維度下之變異。建立最佳製程參數流程後，由相關子計畫負責提供符合可在三維積體電路之薄膜電晶體，經過電路布局設計，互相整合成朝向具高散熱性、高穩定性高品質之三維電路應用於未來顯示科技。
三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I)
(2013)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
三維積體電路(3D IC)關鍵技術之研究
(2009)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
三維積體電路(3D IC)關鍵技術之研究
(2010)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
發展超低溫銅接合與3DIC技術以實現40奈米與0.18微米異質整合平台及先進小尺寸石英震盪元件之研究
(2016)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
發展超低溫銅接合與3DIC技術以實現40奈米與0.18微米異質整合平台及先進小尺寸石英震盪元件之研究
(2015)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
發展超低溫銅接合與3DIC技術以實現40奈米與0.18微米異質整合平台及先進小尺寸石英震盪元件之研究
(2014)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
超高通道與解析度微大腦皮質訊號擷取系統晶片封裝的研發---子計畫二：使用TSV與3D IC技術製作超高通道與解析度微大腦皮質訊號擷取系統晶片
(2016)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
超高通道與解析度微大腦皮質訊號擷取系統晶片封裝的研發---子計畫二：使用TSV與3D IC技術製作超高通道與解析度微大腦皮質訊號擷取系統晶片
(2015)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所
超高通道與解析度微大腦皮質訊號擷取系統晶片封裝的研發---子計畫二：使用TSV與3D IC技術製作超高通道與解析度微大腦皮質訊號擷取系統晶片
(2014)
陳冠能
;
CHEN KUAN-NENG
;
國立交通大學電子工程學系及電子研究所