Browsing by Author "Chang, Chun-Yen"

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52.5% Data Rate Improvement by Employing Volterra Filtering and Exponential Companding in a High Loss Budget and High-Capacity OFDM Long-Reach PON
(2016)
Chen, Hsing-Yu
;
Wei, Chia-Chien
;
Liu, Jun-Jie
;
Hsu, Chia-Wei
;
Wu, Hsin-Yu
An exponential companding method cooperating with Volterra filtering is proposed and demonstrated to substantially improve data rate by 52.5% in a 53.3-Gbps 60-km OFDM LR-PON with 30-dB loss budget based on 10-GHz EAM and PIN.
A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals
(2013-02-01)
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Hung, Min-Feng
;
Tang, Zih-Yun
;
Cheng, Ya-Chi
This work presents gate-all-around (GAA) polycrystalline silicon (poly-Si) nanowires (NWs) channel poly-Si/SiO2/Si3N4/SiO2/poly-Si (SONOS) nonvolatile memory (NVM) with a self-assembled Si nanocrystal (Si-NC) embedded charge trapping (CT) layer. Fabrication of the Si-NCs is simple and compatible with the current flash process. The 2-bit operations based on channel hot electrons injection for programming and channel hot holes injection for erasing are clearly achieved by the localized discrete trap. In the programming and erasing characteristics studies, the GAA structure can effectively reduce operation voltage and shorten pulse time. One-bit programming or erasing does not affect the other bit. In the high-temperature retention characteristics studies, the cell embedded with Si-NCs shows excellent electrons confinement vertically and laterally. With respect to endurance characteristics, the memory window does not undergo closure after 10(4) program/erase (P/E) cycle stress. The 2-bit operation for GAA Si-NCs NVM provides scalability, reliability and flexibility in three-dimensional (3D) high-density flash memory applications. (C) 2013 The Japan Society of Applied Physics
A CMOS distributed amplifier with current reuse optimization
(2006)
Chou, Mei-Fen
;
Tsou, Wen-An
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Dunn, Robert H.
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Huang, Hsiang-Lin
;
Wen, Kuei-Ann
A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption while retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only,12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-mu m CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide.-band transceivers.
A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
A delta-doped InGaP/InGaAs pHEMT with different doping profiles for device-linearity improvement
(2007-07-01)
Lin, Yueh-Chin
;
Chang, Edward Yi
;
Yamaguchi, Hiroshi
;
Wu, Wei-Cheng
;
Chang, Chun-Yen
In this paper, delta-doped InGaP/InGaAs pseudomorphic high-electron-mobility transistors (pHEMTs) with doping-profile modifications are investigated in order to improve the device linearity. The proposed modification was based on the third-order intermodulation distortion (IM3) and the third-order intercept point (IP3) analysis using a simple equivalent circuit of the devices. The correlations of the extrinsic transconductance (Gm) with IM3 and IP3 indicate that the flatness of Gin, as a function of gate-bias causes a lower IM3 level. On the other hand, a high Gm with a flatter Gm distribution results in higher IP3 value for the device. Therefore, doping modifications that improve the flatness of the Gm distribution will also improve the device linearity. Doping modifications in the Schottky layer (Schottky layer doped) and in the channel layer (channel doped) of the conventional delta-doped InGaP/InGaAs pHEMT were investigated. It was also found that extra doping, either in the channel region or in the Schottky layer, improved the flatness of the Gm distribution under different gate-bias conditions. This achieved a lower IM3 and a higher IP3 with a small sacrifice in the peak Gm value. The power performances of these devices were tested at different drain biases. Even though it had the lowest electron mobility among the three different types of devices studied, the channel-doped device demonstrated the best overall linearity performance, the highest IP3 value, the lowest IM3 level, and the best adjacent-channel power ratio under code-division multiple-access modulation.
A fabrication of germanium nanocrystal embedded in silicon-oxygen-nitride layer
(2006)
Tu, Chun-Hao
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Liu, Hsin-Chou
;
Weng, Chi-Feng
The formation of germanium nanocrystals embedded in silicon-oxygen-nitride (SiON) layer acting as distributed charge storage elements is proposed in this work. A large memory window is observed due to the isolated Ge nanocrystals in the SiON gate stack layer. The Ge nanocrystals were nucleated after the high-temperature oxidation of SiGeN layer. The nonvolatile memory device with the Ge nanocrystals embedded in SiON stack layer exhibits 4 V threshold voltage shift under 7 V write operation. Also, the sequent high-temperature oxidation of the SiGeN layer acting as the blocking oxide is proposed to enhance the performance of nonvolatile memory devices. (c) 2006 The Electrochemical Society.
A Flexible IGZO Thin-Film Transistor With Stacked TiO2-Based Dielectrics Fabricated at Room Temperature
(2013-06-01)
Hsu, Hsiao-Hsuan
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Chang, Chun-Yen
;
Cheng, Chun-Hu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter demonstrates the feasibility of full room temperature InGaZnO thin-film transistor (TFT) using trilayer gate dielectric on flexible substrate. Through integrating high-kappa SiO2/TiO2/SiO2 (STS) gate-stack as well as InGaZnO channel thickness modulation, the resulting flexible indium-gallium-zinc oxide (IGZO)/STS TFTs show low threshold voltage of 0.5 V, small subthreshold swing of 0.129 V/decade, high field effect mobility of 76 cm(2)/Vs, and good I-ON/I-OFF ratio of 6.7 x 10(5), which have the potential for the application of high-resolution flexible display.
A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs
(2016)
Cheng, Ya-Chi
;
Chen, Hung-Bin
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Chang, Chun-Yen
;
Cheng, Chun-Hu
;
Shih, Yi-Jia
This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I-on/I-off current ratio (> 10(9)), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.
A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage
(2012-04-01)
Han, Ming-Hung
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Chen, Hung-Bin
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Chang, Chia-Jung
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Wu, Jia-Jiun
;
Chen, Wen-Chong
In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 mu m technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications. (C) 2012 The Japan Society of Applied Physics
A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
;
Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
A Study of Mechanical Lift-Off Technology for High-Efficiency Vertical LEDs Using Micro-Porous GaN Template
(2013-01-01)
Lee, Chia-Yu
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Lin, Da-Wei
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Liu, Che-Yu
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Hsu, Shih-Chieh
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Kuo, Hao-Chung
The high efficiency vertical light emitting diodes (V-LEDs) using mechanical lift-off with Micro-Porous GaN template formed by high temperature molten KOH wet etching process were demonstrated. The average threading dislocation density (TDD) of u-GaN after regrowth was estimated by transmission electron microscopy (TEM) reduced from 2x10(9) to 1x10(8) cm(2). The sapphire substrate was easily removed by mechanical lift-off during wafer bonding process. The light output of V-LEDs are greatly enhanced by 100% compared with Conventional-LEDs at an operating current of 20mA due to the high quality thin GaN and excellent heating dissipation.
A study of resistive switching effects on a thin FeO(x) transition layer produced at the oxide/iron interface of TiN/SiO(2)/Fe-contented electrode structures
(2010-02-01)
Feng, Li-Wei
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Chang, Chun-Yen
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Chang, Yao-Feng
;
Chen, Wei-Ren
;
Wang, Shin-Yuan
Large (>10(2)) and stable resistance switching characteristics were demonstrated in TiN/SiO(2)/Fe structure due to the presence of a thin FeO(x) transition layer at the SiO(2)/Fe interface, produced spontaneously during the plasma-enhanced tetraethyl orthosilicate oxide deposition process. Addition of Pt into Fe electrode, i.e., a TiN/SiO(2)/Fe(0.73)Pt(0.27) structure, was observed to improve the data dispersion of switching parameters, associating with the decrease in Fe content inside the FeO(x) layer. Additionally, current-voltage fitting data shows that current transport mechanism is governed by Ohm's law in low voltage region and Pool-Frenkel behavior in high voltage region, consisting with FeO(x) phase transition characteristics.
A study of resistive switching effects on a thin FeOx transition layer produced at the oxide/iron interface of TiN/SiO2/Fe-contented electrode structures
(2010-02-01)
Feng, Li-Wei
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Chang, Chun-Yen
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Chang, Yao-Feng
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Chen, Wei-Ren
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Wang, Shin-Yuan
Large (>10(2)) and stable resistance switching characteristics were demonstrated in TiN/SiO2/Fe structure due to the presence of a thin FeOx transition layer at the SiO2/Fe interface, produced spontaneously during the plasma-enhanced tetraethyl orthosilicate oxide deposition process. Addition of Pt into Fe electrode, i.e., a TiN/SiO2/Fe0.73Pt0.27 structure, was observed to improve the data dispersion of switching parameters, associating with the decrease in Fe content inside the FeOx layer. Additionally, current-voltage fitting data shows that current transport mechanism is governed by Ohm's law in low voltage region and Pool-Frenkel behavior in high voltage region, consisting with FeOx phase transition characteristics.
Achieving High-Scalability Negative Capacitance FETs with Uniform Sub-35 mV/dec Switch Using Dopant-Free Hafnium Oxide and Gate Strain
(2018-01-01)
Fan, Chia-Chi
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Cheng, Chun-Hu
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Tu, Chun-Yuan
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Liu, Chien
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Chen, Wan-Hsin
For the first time, we successfully demonstrated that the 4-nm-thick dopant-free HfO2 NCFETs using gate strain can implement an energy-efficient switch of a low gate overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. The gate strain favorably rearranges oxygen vacancies and boosts orthorhombic phase transition. Furthermore, the dopant-free HfO2 NCFET can be further improved by in-situ nitridation process. The 4-nm-thick nitrided HfO2 NCFETs achieve a steep symmetric sub-35 mV/dec switch, a sustained sub-40 mV/dec SS distribution, and excellent stress immunity during NC switch. The high-scalability and dopant-free NCFET shows the great potential for the application of future highly-scaled 3D CMOS technology.
AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition
(2017-04-27)
Tzou, An-Jye
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Chu, Kuo-Hsiung
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Lin, I-Feng
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Ostreng, Erik
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Fang, Yung-Sheng
We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 degrees C. The AlN was grown by N-2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H-2/NH3 plasma pretreatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V-DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V-th), corresponding to a 40.2% of current collapse at 150 degrees C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.
Amorphous bilayer TiO2-InGaZnO thin film transistors with low drive voltage
(2014-09-01)
Hsu, Hsiao-Hsuan
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Cheng, Chun-Hu
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Chiou, Ping
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Chiu, Yu-Chien
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Chang, Chun-Yen
This paper describes a high-performance thin-film transistor (TFT) fabricated using TiO2 and InGaZnO semiconducting layers. Favorable transistor characteristics, including a low threshold voltage of 0.45 V, a small subthreshold swing of 174 mV/decade, and a high field effect mobility of 19 cm(2)/V s at a low drive voltage of <2 V, were achieved. This favorable performance mainly resulted from the combined effect of the high-dielectric-constant gate dielectric and the TiO2-InGaZnO active semiconductor bilayer, which reduced the operating voltage, enhanced the device mobility, and improved the transistor gate swing. This TiO2-InGaZnO TFT exhibits great potential for future high-speed and high-resolution display applications. (C) 2014 Elsevier Ltd. All rights reserved.
Amorphous Titanium Oxide Semiconductors on Quasi-Crystal-Like InGaZnO Channels for Thin Film Transistor Applications
(2015-06)
Hsu, Hsiao-Hsuan
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Chiou, Ping
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Cheng, Chun-Hu
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Yen, Shiang-Shiou
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Tung, Chien-Hung
This paper reports an InGaZnO thin-film transistor with titanium-oxide semiconductor as channel capping layer. Based on the experimental results, the titanium-oxide semiconductor has the function of not only a surface passivation layer to reduce the defect states localized at grain boundaries near source/drain contacts, but also a mobility booster to enhance electric field across channel. Compared to control IGZO TFT, the crystalline IGZO TFTs with titanium-oxide semiconductor exhibits an improved performance of a low drive voltage of <5 V, a low threshold voltage of 1.9 V, a low sub-threshold swing of 244 mV/decade, and a high mobility of 13.7 cm(2)/V s. The simple titanium-oxide capping process have been demonstrated in this work, which provides considerable potential for further display applications requiring a low power operation and a low-temperature fabrication.
An analysis of base current effect on the anomalous dip of scattering parameter S(12) in SiGeHBTs
(2005)
Chen, Han-Yu
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chang, Chun-Yen
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電子工程學系及電子研究所
In this paper, the anomalous dip in scattering parameters S(12) of SiGe HBTs is explained quantitatively for the first time. It was found that under constant collector-emitter voltage (V(CE)), an increase of base current (which corresponds to an increase of base-emitter capacitance (C pi) enhances the anomalous dip.
An Investigation of Carbon-Doping-Induced Current Collapse in GaN-on-Si High Electron Mobility Transistors
(2016-06-01)
Tzou, An-Jye
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Hsieh, Dan-Hua
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Chen, Szu-Hung
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Liao, Yu-Kuang
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Li, Zhen-Yu
This paper reports the successful fabrication of a GaN-on-Si high electron mobility transistor (HEMT) with a 1702 V breakdown voltage (BV) and low current collapse. The strain and threading dislocation density were well-controlled by 100 pairs of AlN/GaN superlattice buffer layers. Relative to the carbon-doped GaN spacer layer, we grew the AlGaN back barrier layer at a high temperature, resulting in a low carbon-doping concentration. The high-bandgap AlGaN provided an effective barrier for blocking leakage from the channel to substrate, leading to a BV comparable to the ordinary carbon-doped GaN HEMTs. In addition, the AlGaN back barrier showed a low dispersion of transiently pulsed I-D under substrate bias, implying that the buffer traps were effectively suppressed. Therefore, we obtained a low-dynamic on-resistance with this AlGaN back barrier. These two approaches of high BV with low current collapse improved the device performance, yielding a device that is reliable in power device applications.
An Oxygen Gettering Scheme for Improving Device Mobility and Subthreshold Swing of InGaZnO-Based Thin-Film Transistor
(2014-09-01)
Hsu, Hsiao-Hsuan
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Chang, Chun-Yen
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Cheng, Chun-Hu
;
Chiou, Shan-Haw
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Huang, Chiung-Hui
This study involved developing a low-power and high-mobility metal-oxide thin-film transistor that incorporated a bilayer IGZO/IGZO:Ti semiconductor material. Compared with control metal-oxide TFTs, the bilayer IGZO TFT through thickness modulation of IGZO: Ti can reach the smallest subthreshold swing (85 mV/decade) and the highest field effect mobility (49 cm(2)/Vs) at a drive voltage of <3 V. This performance level improvement can be attributed to the gettering effect caused by the IGZO: Ti capping layer and its dual advantages, which enhance device mobility and improve gate swing.