Browsing by Author "Cheng, CF"

Now showing 1 - 9 of 9

3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOS
(2004)
Yu, DS
;
Chin, A
;
Laio, CC
;
Lee, CF
;
Cheng, CF
For the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
A novel program-erasable high-(K) A1N-Si MIS capacitor
(2005-03-01)
Lai, CH
;
Chin, A
;
Hung, BF
;
Cheng, CF
;
Yoo, WJ
We demonstrate a programmable-erasable MIS capacitor with a single layer high-kappa AIN dielectric on Si having a high capacitance density of 5 fF/mum(2). It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al2O3, AION, or other known high-kappa dielectric capacitors, where the threshold voltage (T h) shifts continuously with voltage. This device exhibits good data retention with a V-th change of only 0.06 V after 10 000 s.
Bias-temperature instability on fully silicided-germanided gates/high-k Al2O3CMOSFETs
(2005)
Liao, CC
;
Yu, DS
;
Cheng, CF
;
Chin, A
;
電子工程學系及電子研究所
We have studied bias-temperature instability (BTI) on fully nickel-silicided (NiSi) and germanided (NiGe) gates on high-k Al2O3 n metal oxide semiconductor field effect transistors (MOSFETs) and pMOSFETs, respectively. At an equivalent oxide thickness of 1.7 nm, the NiSi/Al2O3 pMOSFETs and NiGe/Al2O3 nMOSFETs have a comparable threshold voltage (V-t) change of -34 and 33 mV at 85&DEG; C and 10 MV/cm stress for 1 h. This result is different from the more severe negative BTI (NBTI) degradation measured in oxynitride pMOSFET than positive BTI (PBTI) in nMOSFET. The extrapolated maximum voltage for 10 years' lifetime is 1.16 and -1.12 V from NiSi-NiGe/Al2O3 complementary MOSFETs (CMOSFETs) that can barely meet the required 1 V operation with 10% safety margin. Further improvement is still required because the 1.8 nm oxynitride CMOSFETs have higher 10 years' lifetime operation voltages of 2.48 and -1.52 V for PBTI and NBTI, respectively. © 2005 The Electrochemical Society. All rights reserved.
Novel SiO2/AlN/HfAlO/IrO2 memory with fast erase, large triangle V-th and good retention
(2005)
Lai, CH
;
Chin, A
;
Chiang, KC
;
Yoo, WJ
;
Cheng, CF
Using the strong trapping capability of novel AlN (kappa=10), low voltage drop in high-kappa layers and high workfunction IrO2 with low leakage current, the SiO2/AlN/HfAlO(K=17)/IrO2 device shows good 85 degrees C memory integrity of fast 100 is erase, large 3.7V Delta V-th and 1.9V extrapolated memory window for 10-year retention at low 13V program/erase. These increase to 5.5V Delta V-th and 3.4V for 85 degrees C 10-year retention at 1 ms erase.
Reducing AC power consumption by three-dimensional integration of Ge-on-insulator CMOS on 1-poly-6-metal 0.18 mu m Si MOSFETs
(2005)
Yu, DS
;
Liao, CC
;
Chen, CC
;
Lee, CF
;
Cheng, CF
We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) 0.18 mu m Si devices, where little performance degradation was measured in the lower layer 0.18 mu m Si MOSFETs, due to the inherent low thermal budget (500 degrees C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach. (c) 2005 The Electrochemical Society. All rights reserved.
The copper contamination effect of Al2O3 gate dielectric on Si
(2004)
Liao, CC
;
Cheng, CF
;
Yu, DS
;
Chin, A
;
電子工程學系及電子研究所
We have studied the Cu contamination effect on 4.2 nm thick Al2O3 metal-oxide semiconductor (MOS) capacitors with an equivalent-oxide thickness (EOT) of 1.9 nm. In contrast to the large degradation of gate oxide integrity of control 3.0 nm SiO2 MOS capacitors contaminated by Cu, the 1.9 nm EOT Al2O3 MOS devices have good Cu contamination resistance with only small degradation of gate dielectric leakage current, charge-to-breakdown, and stress-induced leakage current. This strong Cu contamination resistance is similar to oxynitride (with high nitrogen content), but the Al2O3 gate dielectric has the advantage of higher K value and lower gate dielectric leakage current. (C) 2004 The Electrochemical Society.
The effect of IrO2-IrO2-Hf-LaAlO3 gate dielectric on the bias-temperature instability of 3-d GOI CMOSFETs
(2005-06-01)
Yu, DS
;
Liao, CC
;
Cheng, CF
;
Chin, A
;
Li, MF
We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-κ/Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 μ m CMOSFETs. The devices used IrO2-IrO2-Hf dual gates and a high-κ LaAlO3 gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-κ/GOI p-and n-MOSFETs displayed threshold voltage (V-t) shifts of 30 and 21 mV after 10 MV/cm, 85 &DEG; C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-κ-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.
Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices
(2005-02-01)
Yu, DS
;
Chin, A
;
Liao, CC
;
Lee, CF
;
Cheng, CF
We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.
Very high kappa and high density TiTaO MIM capacitors for analog and RF applications
(2005)
Chiang, KC
;
Chin, A
;
Lai, CH
;
Chen, WJ
;
Cheng, CF
For the first time, high density (10.3 fF/mu m(2)), low voltage linearity (alpha = 89 ppm/V-2) and small leakage current (1.2 x 10(-8) A/cm(2) or 5.8 fA/[pF circle V] at 2V) meet all the ITRS requirements of analog capacitor at year 2018. These are achieved by novel high-kappa TiTaO (kappa = 45) and high work-function Ir capacitor, which further improve to very high 23 fF/mu m(2) density and low 81 ppm/V-2 linearity for higher speed analog/RF ICs at 1 GHz, using the fast a decay mechanism with increasing frequency.