Browsing by Author "Chien, Chao-Hsin"

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3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor
(2016)
Chou, Chen-Han
;
Hsu, Chung-Chun
;
Yeh, Wen-Kuan
;
Chung, Steve S.
;
Chien, Chao-Hsin
We propose a new device structure, namely CAA T-FinFET, for 10nm MOSFETs with using contact all around (CAA) structure. According to 3D simulation study, the CAA T-FinFET possess many advantages over the conventional FinFET structure, such as short channel effect (SCE) suppression by self-aligned oxide (SA oxide), parasitic leakage path isolation with body-tied bulk, sourceldrain series resistance reducing and fin to fin pitch scaling by contact all around process. Base on heterogeneous bulk for strain application, CAA T-FinFET has better electrical performance and easy process control. All these advantages are achieved by depositing a self-aligned oxide after isotropic etching in SID region. Contact all around can efficiently solve the series resistance degradation and pitch scaling by replacing diamond-shape SID stressor with the full contact metal. CAA T-FinFET has high potential to be applied to the varied heterogeneous substrate and high mobility channel (Ge and III-V) MOSFETs by SA oxide.
3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect Transistor
(2015)
Chou, Chen-Han
;
Hsu, Chung-Chun
;
Chung, Steve S.
;
Chien, Chao-Hsin
;
電子工程學系及電子研究所
We propose a novel device structure, namely T-FinFET, for sub-14nm MOSFET with using lighter anti punch through (APT) implant. According to 3D TCAD simulation, the T-FinFET is found to posses many advantages over the normal FinFET, such as better short channel effect (SCE) and drain induced barrier lowering (DIBL), having smaller S/D capacitance and junction leakage and fewer masks. Compared to gate-all-around (GAA) structure, the T-FinFET also has compatible electrical performance. All these features are obtained by depositing a self-aligned (SA) oxide after recessing the Si fin in the S/D region. It can be applied to Ge and III-V MOSFETs for suppressing the SCEs and S/D leakage, arising from higher permittivity and lower band gap than Si.
A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications
(2012-04-01)
Chen, Min-Cheng
;
Chen, Hao-Yu
;
Lin, Chia-Yi
;
Chien, Chao-Hsin
;
Hsieh, Tsung-Fan
This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.
A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
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Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
(2011-11-01)
Chen, Hou-Yu
;
Chen, Chun-Chi
;
Hsueh, Fu-Kuo
;
Liu, Jan-Tsai
;
Shy, Shyi-Long
For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
A study of bulk current mechanism in P3HT-based thin film transistors and approach for current suppression
(2012-11-01)
Chang, Chia-Hao
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Chien, Chao-Hsin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this article, poly(3-hexylthiophene) (P3HT) based thin film transistors with Ti capped source and drain electrodes (S/D) was employed to have an insight into the mechanism of bulk current effect, which led to poor subthreshold swing and large off current. Our newly developed PTFTs do show greater characteristics in the aspects of on/off current ratio and subthreshold swing than those with the conventional Au/Ti S/D. In order to explain the results, we propose that the bulk current is composed of two components, i.e., side-wall and top-face injections. We ascribe the improvements to the reduction of top-face injection bulk current due to the larger injection barrier between the P3HT and Ti. As comparing the PTFTs with Ti capped laterally grown multi-wall carbon nanotube (MWCNT) S/D with the PTFTs with MWCNT S/D, we also observe similar tendency of bulk current reduction. From the viewpoint of device operation, better subthreshold swing and smaller off current result in faster device switching and lower power consumption. By this new approach of S/D structure, there are two and 20 times improvements on the subthreshold swing and off current, respectively, although the reduction of the bulk current also leads to a slight decrease of the on-current. (C) 2012 Elsevier B.V. All rights reserved.
An Investigation of Transient Effects in Poly(3-hexylthiophenes) Based Thin Film Transistors Caused by Oxygen and Water Molecules
(2011)
Chang, Chia-Hao
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Chen, Meng-Fei
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Chien, Chao-Hsin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this article, we investigate hysteresis behavior observed in the current-voltage transfer curve of regioregular poly(3-hexylthiophene)(P3HT) based thin film transistors (PTFTs) using bi-directional voltage sweeping. According to the results of our experiments, the hysteresis effects were closely related to oxygen (O(2)) and water (H(2)O) molecules residing in the P3HT active layer. As a result, we hypothesized that O(2) and H(2)O in the P3HT could form two kinds of dopants, i.e., stable and transient states. Stable state dopants, which are commonly thought to be of the acceptor-type dopants, could induce holes in the channel region contributing to better on-current. On the contrary, transient state dopants were found to be unable to induce holes, however could enable the formation of polarization agents and create hysteresis. These two types of dopants seem have a common origin, thus they could be converted into each other through the combination of specific processes and applied external bias. From the viewpoint of device operation stability, except on-current level and characteristics including threshold voltage, off-current magnitude and on/off ratio, the impact of hysteresis should garner the attention of those pursuing high performance PTFTs. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3604963] All rights reserved.
An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3
(2008)
Lai, Sheng-Chih
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Lue, Hang-Ting
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Liao, Chien-Wei
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Huang, Yu-Fong
;
Yang, Ming-Jui
The role of Al2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, Al2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, Al2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO tunneling layers, provides efficient channel hole injection for erase. BE-MANOS [2] should be an ideal combination with fast erase and good reliability. However, it shows poor data retention. By inserting a SiO2 buffer layer between Al2O3 and the SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability. The EOT scalability is also investigated.
Applying Dielectrophoresis on Silver Nanowires Alignment and Assembly to Enhance the Efficiency of Plasmonic Silicon Solar Cells
(2015-09-01)
Lin, Ching-Chang
;
Wang, Szu-Yu
;
Lin, Wei-Ling
;
Lin, Ya-Lin
;
Cheng, Chieh
The enhancement effects for solar cell are examined on the plasmonic properties of Ag nanowires (AgNWs) arrays, which fabricated by dielectrophoresis techniques. AgNWs in 100 nm diameters with aspect ratio (AR) of 100 were assembled into an array between the micrometer spaced electrodes by applying an AC electric field. The simulating results show that the array AgNWs can enhance the localized surface electric field on the silicon surface efficiently. Since, the incident lights can be scattered and trapped in the silicon layers which improves the enhancement of the external quantum efficiency. The optimized result of alignment of AgNWs average angle are 89.17 degree to the electrode edges and 21.98 degree of standard deviation under 100 Vpp, 250 kHz. In addition, the reflectance is 18.4% lower than those without AgNWs ones. The optimized plasmonic solar cells increase efficiency from 7.78% to 8.72%.
Architecture of a n-type metal-oxide-semiconductor transistor with a compressive strained silicon-germanium channel fabricated on a silicon (110) substrate
(2007-09-06)
Luo, Guangli
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Chien, Chao-Hsin
;
Yang, Tsung-Hsi
;
Chang, Chun-Yen
The present invention discloses an architecture of a NMOS transistor with a compressive strained Si—Ge channel fabricated on a silicon (110) substrate, which comprises: a p-silicon (110) substrate, two n+ ion-implanted regions functioning as the source and the drain respectively, a compressive strained Si—Ge channel layer, and a gate structure. The compressive strained Si—Ge channel layer is grown on the p-silicon (110) substrate to reduce the electron conductivity effective mass in the [1_l -10] crystallographic direction and to promote the electron mobility in the [1-10] crystallographic direction. Thus, the present invention can improve the electron mobility of a NMOS transistor via the channels fabricated on the silicon (110) substrate. Further, the NMOS transistor of the present invention can combine with a high-speed PMOS transistor on a silicon (110) substrate to form a high-performance CMOS transistor on the same silicon (110) substrate.
Body-Tied Germanium FinFETs Directly on a Silicon Substrate
(2012-12-01)
Chen, Che-Wei
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Chung, Cheng-Ting
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Luo, Guang-Li
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Chien, Chao-Hsin
;
電子工程學系及電子研究所
We fabricated body-tied Ge p-channel fin field-effect transistors (p-FinFETs) directly on a Si substrate with a high-kappa/metal gate stack. This scheme is fully compatible with Si standard processing. The FinFET structure has excellent control on the channel potential and thus can improve the short-channel effect. The diode with p(+)-Ge/n-Si heterojunctions illustrates a remarkably high I-ON/I-OFF > 10(6) despite the presence of misfit dislocations at the interface. The high-hole-mobility body-tied Ge p-FinFETs with a fin width W-Fin of similar to 40 nm and a mask channel length L-Mask of 120 nm depict a driving current of 22 mu A/mu m at V-G = -2 V and a low OFF-current of 3 nA/mu m at V-G = 2 V. The subthreshold characteristics with a swing of 228 mV/dec and drain-induced barrier lowering of 288 mV/V are demonstrated.
Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel
(2014-01-01)
Chen, Che-Wei
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Chung, Cheng-Ting
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Tzeng, Ju-Yuan
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Chang, Pang-Sheng
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Luo, Guang-Li
In this letter, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I-ON/I-OFF ratio and good short channel effect control on the channel potential. The current ratio is of similar to 6 x 10(3) (I-D) at V-DS = -0.1 V, V-GS = -3, and 0 V. The relatively low OFF-current is of 6 nA/ mu m at V-DS = -0.1 V and V-GS = 0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L-G = 120 nm.
Cerium oxide nanocrystals for nonvolatile memory applications
(2007-12-24)
Yang, Shao-Ming
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Chien, Chao-Hsin
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Huang, Jiun-Jia
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Lei, Tan-Fu
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Tsai, Ming-Jinn
The characteristics of silicon-oxide-nitride-oxide-silicon-type memories embedded with cerium oxide nanocrystals were demonstrated. They were fabricated by depositing a thin CeO(2) film on the SiO(2) tunneling layer and subsequently rapid-thermal annealing process. The mean size and aerial density of the CeO(2) nanocrystals embedded in SiO(2) are estimated to be about 8-10 nm and (3-7)x10(11)/cm(-2) after a high-temperature annealing with different ambients on 900 degrees C. The program/erase behaviors and data retention characteristics were described to demonstrate its advantages for nonvolatile memory device applications. (c) 2007 American Institute of Physics.
Characteristics of atomic-layer-deposited Al(2)O(3) high-k dielectric films grown on Ge substrates
(2008)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
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Liu, Jun-Cheng
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Kei, Chi-Chung
This paper describes the structural and electrical properties of Al(2)O(3) thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300 degrees C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al(2)O(3) film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al(2)O(3) and interfacial GeO(2) appeared at temperatures above 200 degrees C, along with degradation of the GeO(2)/Ge interface. Accordingly, a relatively large gate leakage current (J(g)) and a high density of interfacial states D(it) (> 10(13) cm(-2) eV(-1)) were observed as a result of deterioration of the entire Al(2)O(3)/Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600 degrees C in a N(2) ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO(x) volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H(2)/N(2), 1:10) at low temperature (300 degrees C) improved the capacitance-voltage characteristics of the Pt/Al(2)O(3)/Ge structure, in terms of providing a lower value of D(it) (ca. 6 x 10(11) cm(-2) eV(-1)), a lower value of J(g), and a reduced hysteresis width.
Comparison of the Physical and Electrical Properties of HfO2/Al2O3/HfO2/GeOx/Ge and HfO2/Al2O3/GeOx/Ge Gate Stacks
(2019-08-01)
Tsai, Yi-He
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Chou, Chen-Han
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Li, Hui-Hsuan
;
Yeh, Wen-Kuan
;
Lino, Yu-Hsien
A high-quality HfGeOx interfacial layer (IL) was formed in a HfO2/Al2O3/HfO2/GeOx gate stack through thermal annealing. The diffusing of GeO into the HfO2 layer led to the mixing of the GeOx and HfO2 layers, as identified through energy-dispersive X-ray Spectroscopy (EDX). X-ray photo-electron spectroscopy (XPS) data for HfGeOx IL confirmed the formation of Ge-O-Hf bonds owing to the induced shift of the Ge3d(ox) spectra to lower binding energies. The electrical and reliability data indicated that the capacitor with HfGeOx IL presented not only lower interface states density (Dit, approximately 7 x 10(11) eV(-1)cm(-2)) but also less Dit increment (approximately 3 x 10(11) eV(-1)cm(-2)) after stressing than did the capacitor without the HfGeOx IL. Moreover, the Ge p-metal-oxide-semiconductor field-effect transistor HfGeOx IL exhibited a high effective hole mobility (approximately 704 cm(2)/V . s).
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
(2019-12-01)
Chung, Yun-Yan
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Lu, Kuan-Cheng
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Cheng, Chao-Ching
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Li, Ming-Yang
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Lin, Chao-Ting
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer
(2019-02-01)
Tsai, Yi-He
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Chou, Chen-Han
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Chung, Yun-Yan
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Yeh, Wen-Kuan
;
Lin, Yu-Hsien
HfO2-based gate stacks with titanium (Ti) incorporated into a GeOx interfacial layer (IL) were fabricated on p-Ge substrates. X-ray photoelectron spectroscopy results, incorporating Ti, can efficiently suppress the GeO volatilization. This contributed to achievement of an equivalent oxide thickness of approximately 0.8 nm, a low interface states density D-it of approximately 2.5 x 10(11) eV(-1)cm(-2), and a smaller D-it increment of approximately 1 x 10(11) eV(-1)cm(-2) after constant negative voltage stress at a field of 8 MV/cm. Therefore, Ti is appropriate for improving the quality of GeOx through high temperature annealing.
Effect of Mg Doping on the Electrical Characteristics of High Performance IGZO Thin Film Transistors
(2014)
Wu, Hung-Chi
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Liu, Tung-Sheng
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Chien, Chao-Hsin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we report that the electrical characteristics of Indium-Gallium-Zinc-Oxide Thin Film Transistors (IGZO-TFTs) can be improved by Mg doping in the IGZO layer. Several composite IGZO/Mg-doped IGZO channel structures were employed. With appropriate Mg-doped IGZO thickness, the electrical properties such as mobility, subthreshold swing (S.S.) and on/off ratio can be significantly improved by Mg doping. Mg doping in IGZO layer can stabilize device performance whatever the device is stressed under positive gate bias or negative gate bias with illumination. By X-ray photoelectron (XPS) analysis, we observe the presence of Mg can change the oxygen bonding states and influence the properties of IGZO layer. The atomic percentage of Mg in the IGZO layer is about 6.53%. As a result, Mg doping is a useful method to enhance the performance and stability of IGZO-TFTs. (C) 2013 The Electrochemical Society. All rights reserved.
Effect of passivation layer on InGaZnO thin-film transistors with hybrid silver nanowires as source and drain electrodes
(2015-08-01)
Yu, Chien-Hsien
;
Wu, Hung-Chi
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Chien, Chao-Hsin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
InGaZnO (IGZO) thin-film transistors (TFTs) with hybrid silver nanowires (hybrid-AgNWs) as the source and drain electrodes exhibit superior performance according to the on/off current ratio (approximate to 10(6)), subthreshold swing (SS) (367 mV/decade), and mobility (15.6 cm(2) V-1 s(-1)). The transfer and output characteristics of nanowire-based electrodes are comparable with those of titanium electrodes. The devices are fabricated on a plastic substrate and are highly transparent (>70%) and flexible. The device performance is severely degraded during operation in air, especially under high humidity conditions, and progressive deterioration resulting from water molecule diffusion leads to a high current density when the device is swept. Hence, introducing a passivation layer on the hybrid-AgNW electrodes is imperative. (C) 2015 The Japan Society of Applied Physics
Effects of HfO(2) buffer layer thickness on the properties of Pt/SrBi(2)Ta(2)O(9)//HfO(2)/Si structure
(2008-07-01)
Leu, Ching-Chich
;
Lin, Chen-Han
;
Chien, Chao-Hsin
;
Yang, Ming-Jui
;
電子工程學系及電子研究所
We investigated structural and characteristic changes in thin HfO(2) films (< 10 nm) by varying their thicknesses and also examined their influence on the properties of Pt/SrBi(2)Ta(2)O(9)/HfO(2)/Si metal/ferroelectric/insulator/semiconductor (MFIS) structures. HfO(2) films with different thicknesses were found to exhibit rather distinct characteristics and to profoundly affect the properties of the fabricated MFIS capacitor. We found that, when employing 3.2-nm-thick HfO(2) as the buffer layer, the MFIS capacitor showed good memory performance at low operation voltage. However, this study demonstrated that some of the HfO(2) limited its application in MFIS memory, even though it is the most promising alternative gate dielectric material.