Browsing by Author "Chin, A"

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3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOS
(2004)
Yu, DS
;
Chin, A
;
Laio, CC
;
Lee, CF
;
Cheng, CF
For the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
40-GHz coplanar waveguide bandpass filters on silicon substrate
(2002-11-01)
Chan, KT
;
Chen, CY
;
Chin, A
;
Hsieh, JC
;
Liu, J
We report a very simple process to fabricate high performance filter on Si at 40 GHz; using proton implantation. The filter has only -3.4-dB loss at peak transmission of 40 GHz; with a broad 9-GHz bandwidth. In sharp contrast, the filter on 1.5-mum SiO2 isolated Si has much worse transmission and reflection loss. This is the first demonstration of high performance filter at millimeter-wave regime on Si with process compatible to current VLSI technology.
A fully planar microstrip coupled-line coupler with a high coupling level
(2005-07-20)
Chen, CC
;
Kuo, JT
;
Jiang, M
;
Chin, A
;
傳播研究所
A fully planar microstrip coupler with a high coupling level tip to 4 dB is fabricated on PCB. Based on the conventional coupled-line structure, a gap Size of coupled lines about 14 mu m is realized by low cost IC process. It has a single stage and requires no bond wire. In measurement, a bandwidth more than 50% and isolation and return loss better than -20 dB are achieved. The measured responses have good agreement with EM simulation data. (c) 2005 Wiley Periodicals, Inc.
A high-density MIM capacitor (13 fF/mu m(2)) using ALD HfO2 dielectrics
(2003-02-01)
Yu, XF
;
Zhu, CX
;
Hu, H
;
Chin, A
;
Li, MF
Metal-insulator-metal (MIM) capacitors with a different thickness of HfO2 have been investigated. The results show that both the capacitance density and voltage coefficients of capacitance (VCCs) increase with decreasing the HfO2 thickness. In addition, it is also found that the VCCs decrease logarithmically with increasing the thickness Of HfO2. Furthermore, the MIM capacitor with 10-nm HfO2 shows a record high capacitance density of 13 fF/mum(2) and a VCC of 607 ppm/V, which can meet the requirement of the International Technology Roadmap for Semiconductors. It can also provide a low leakage current of 5.95 x 10-(8)A/cm(2) at room temperature at I V, low tangent values below 0.05, and a small frequency dependence as well. All these indicate that it is very suitable for use in silicon integrated circuit applications.
A novel program-erasable high-(K) A1N-Si MIS capacitor
(2005-03-01)
Lai, CH
;
Chin, A
;
Hung, BF
;
Cheng, CF
;
Yoo, WJ
We demonstrate a programmable-erasable MIS capacitor with a single layer high-kappa AIN dielectric on Si having a high capacitance density of 5 fF/mum(2). It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al2O3, AION, or other known high-kappa dielectric capacitors, where the threshold voltage (T h) shifts continuously with voltage. This device exhibits good data retention with a V-th change of only 0.06 V after 10 000 s.
A quantum trap MONOS memory device using AlN
(2006)
Lai, CH
;
Wu, CH
;
Chin, A
;
Wang, SJ
;
McAlister, SP
We report a IrO2-HfAlO-AlN-SiO2-Si MONOS device that displays excellent characteristics in terms of speed (100 mu s at +/- 13 V for program/erase) and memory window (3.7 V) at 85 degrees C operation. This device also shows good 10-year extrapolated data retention with a large 1.9 V window at 85 degrees C. The achieved performance compares well with the best reported memory device data. (c) 2006 The Electrochemical Society.
A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivation
(2004-09-01)
Wu, N
;
Zhang, QC
;
Zhu, CX
;
Chan, DSH
;
Du, AY
In this letter, we demonstrate a novel surface passivation process for HfO2 Ge pMOSFETs using SiH4 surface annealing prior to HfO2 deposition. By using SiH4 passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO2 Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a similar to 140% higher peak mobility than that of the device with surface nitridation.
A tunable and program-erasable capacitor on Si with excellent tuning memory
(2004)
Lai, CH
;
Lee, CF
;
Chin, A
;
Zhu, C
;
Li, MF
A novel tunable and program-erasable high-kappa: AIN MIS capacitor is demonstrated for the first time with excellent tuning memory, which is useful to tune the impedance mismatching and resonance frequency without always connected voltage bias circuit. Large C-max /C-min tunability of 12 is obtained due to the high-kappa AIN dielectric with high 5 muF/mum(2) capacitance density. Good tuning memory is evidenced from the small V-th variation after program or erase at +4 V or -4 V for 10,000 s and the potential of years long extrapolated memory time.
AC power loss and signal coupling in very large scale integration backend interconnects
(2006-04-01)
Chen, CC
;
Kao, HL
;
Liao, CC
;
Chin, A
;
McAlister, SP
Both the coupling and AC power losses in integrated circuit interconnects in the radio-frequency regime have been measured. The AC power loss decreases with decreasing length, decreasing spacing, and increasing inter metal dielectric (IMD) thickness of parallel metal lines. The unwanted signal coupling and cross-talk monotonically decrease with increasing spacing and decreasing length of the parallel metal lines. However, increasing the IMD thickness from 0.7 to 6 mu m improves the low frequency performance but not the maximum operation frequency. Using a high-resistivity Si (HRS) substrate the AC power loss is significantly reduced but is traded off with an increase in coupling loss. The most effective method of reducing both the AC power and coupling losses is the combined use of three dimensional (3D) integration and an HRS, which gives larger than 1-2 orders of magnitude improvement, up to 20 GHz.
Al2O3-Ge-On-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates
(2004-03-01)
Yu, DS
;
Huang, CH
;
Chin, A
;
Zhu, CX
;
Li, MF
High-kappa, A1(2)O(3)/Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the A1(2)O(3)-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with A1(2)O(3)-Si MOSFETs. Additionally, A1(2) O-3-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than A1(2)O(3)-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500 degreesC rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-kappa to minimize interfacial reactions and crystallization of the high-kappa material, and oxygen penetration in high-kappa MOSFETs.
Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric
(2004-11-01)
Wu, N
;
Zhang, QC
;
Zhu, CX
;
Chan, DSH
;
Li, MF
An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The surface SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition. The electrical measurement shows that an equivalent oxide thickness of 13.5 Angstrom and a leakage current of 1.16x10(-5) A/cm(2) at 1 V gate bias was achieved for TaN/HfO2/Ge MOS capacitors with the SiH4 surface treatment. (C) 2004 American Institute of Physics.
Bi3.25La0.75Ti3O12 thin films on ultrathin Al2O3 buffered Si for ferroelectric memory application
(2002-04-29)
Chen, SY
;
Sun, CL
;
Chen, SB
;
Chin, A
;
材料科學與工程學系
We have investigated the physical and electrical properties of Bi3.25La0.75Ti3O12 (BLT) thin films on Pt/Ti/SiO2/Si and on Al2O3(6 nm)/Si, which are used for one-transistor-one-capacitor and one-transistor ferroelectric memory, respectively. The BLT thin films on both substrates show good capacitance-voltage characteristics and the same threshold voltage shift of 1.6 V at applied +/-10 V bias. However, the leakage current of BLT on Al2O3/Si at -100 kV/cm is two orders of magnitude lower than that on Pt. The comparable memory characteristics and much reduced leakage current of BLT on Al2O3/Si are the strong advantages as compared with BLT on Pt because it is directly related to switching energy and device scaling down. (C) 2002 American Institute of Physics.
Bias-temperature instability on fully silicided-germanided gates/high-k Al2O3CMOSFETs
(2005)
Liao, CC
;
Yu, DS
;
Cheng, CF
;
Chin, A
;
電子工程學系及電子研究所
We have studied bias-temperature instability (BTI) on fully nickel-silicided (NiSi) and germanided (NiGe) gates on high-k Al2O3 n metal oxide semiconductor field effect transistors (MOSFETs) and pMOSFETs, respectively. At an equivalent oxide thickness of 1.7 nm, the NiSi/Al2O3 pMOSFETs and NiGe/Al2O3 nMOSFETs have a comparable threshold voltage (V-t) change of -34 and 33 mV at 85&DEG; C and 10 MV/cm stress for 1 h. This result is different from the more severe negative BTI (NBTI) degradation measured in oxynitride pMOSFET than positive BTI (PBTI) in nMOSFET. The extrapolated maximum voltage for 10 years' lifetime is 1.16 and -1.12 V from NiSi-NiGe/Al2O3 complementary MOSFETs (CMOSFETs) that can barely meet the required 1 V operation with 10% safety margin. Further improvement is still required because the 1.8 nm oxynitride CMOSFETs have higher 10 years' lifetime operation voltages of 2.48 and -1.52 V for PBTI and NBTI, respectively. © 2005 The Electrochemical Society. All rights reserved.
Broad-spectrum light emission at microscopic breakdown sites in metal-insulator-silicon tunnel diodes
(2005-09-01)
Mihaychuk, JG
;
Denhoff, MW
;
McAlister, SP
;
McKinnon, WR
;
Chin, A
In addition to Si band-edge electroluminescence (EL) near 1.1 eV, we observe hot-electron EL in metal-insulator-silicon tunnel diodes that can span a detector-limited range from 0.7 to 2.6 eV (1780-480 nm). The maximum photon energy increases with increasing forward bias. In one implementation, sub-micron-sized EL sites appear during the forward-bias stress. The number of sites grows linearly with the current, consistent with the dielectric breakdown of the insulator. We compare the poststress current-voltage data with the quantum-point-contact model. Results are presented for various p-type Si(100) devices having 2-8-nm-thick SiO2, Al2O3, and HfOxNy insulators. We also describe devices in which electron-beam lithography of an 18-nm-thick SiO2 is used to define EL sites. (c) 2005 American Institute of Physics.
Characteristics of Pb(Zr0.53Ti0.47)O-3 on metal and Al2O3/Si substrates
(2001-11-01)
Sun, CL
;
Chen, SY
;
Yang, MY
;
Chin, A
;
材料科學與工程學系
We have fabricated Pb(Zr0.53Ti0.47)O-3 on Pt and Pb(Zr0.53Ti0.47)O-3 on 4 nm Al2O3/Si substrates. Although Pb(Zr0.53Ti0.47)O-3 on Pt has a larger dielectric constant and grain size than those on Al2O3/Si, the Pb(Zr0.53Ti0.47)O-3 thin films on both substrates show good capacitance-voltage characteristics and the same threshold voltage shift of similar to3.6 V. Moreover, the leakage current density of Pb(Zr0.53Ti0.47)O-3 on Al2O3/Si at -10 V is nearly three orders of magnitude lower than that of Pb(Zr0.53Ti0.47)O-3 on Pt. The comparable memory characteristics and the lower leakage current of Pb(Zr0.53Ti0.47)O-3 on Al2O3/Si are important for continuous scaling down the ferroelectric memory. (C) 2001 The Electrochemical Society.
Characterization of Si/SiGe heterostructures on Si formed by solid phase reaction
(2002-03-01)
Huang, CH
;
Chin, A
;
Chen, WJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have characterized the Si/Si(0.6)Ge(0.4) heterostructure formed by two-step solid-phase reaction. Single crystalline behavior is evidenced by X-ray diffraction. In sharp contrast to conventional strain-relaxed SiGe, an extremely smooth surface close to the Si substrate is measured by cross-sectional transmission electron microscopy and atomic force microscopy. Good material quality is further evidenced from the near identical current-voltage characteristics for thermal oxide grown on Si/Si(0.6)Ge(0.4) and on the Si control sample. (C) 2002 The Electrochemical Society.
Cu contamination effect in oxynitride gate dielectrics
(2001-11-01)
Lin, YH
;
Pan, FM
;
Liao, YC
;
Chen, YC
;
Hsieh, IJ
We have studied the effect of Cu contamination in oxynitride gate dielectrics. Compared to thermal SiO2 with a physical thickness of 3-5 nm, the oxynitride shows a much improved Cu contamination resistance. Furthermore, the Cu contamination resistance increases with increasing nitrogen content. The mechanism of improved gate dielectric resistance to Cu is due to the strong diffusion barrier properties of oxynitride as observed by secondary ion mass spectroscopy. (C) 2001 The Electrochemical Society.
Deuterium effect on stress-induced leakage current
(1999-04-01)
Lin, BC
;
Cheng, YC
;
Chin, A
;
Wang, T
;
Tsai, C
We have studied and compared stress-induced leakage current in oxides subjected to H-2 and D-2 annealing. There is not much difference in stress-induced leakage current between thick 70-Angstrom-oxides annealed by these two isotopes. In sharp contrast, an improvement of several-fold in stress-induced leakage current is observed in 27-Angstrom-thick oxides annealed in D-2 ambient compared to that annealed in H-2. The significant improvement in this direct-tunneling oxide may be due to the passivation of intrinsic defects and dangling bonds in a transition SiOx layer.
Device level characterization for energy bandgap of strain-relaxed SiGe and oxide/SiGe barrier height
(2004)
Huang, CH
;
Yu, DS
;
Chin, A
;
Chen, WJ
;
McAlister, SP
From the interface state density with energy plot measured by capacitance-voltage characteristics, we have derived the energy bandgap of strain-relaxed Si1-xGex (x: 0.4 and 0.7) for the first time at the device level, because the allowed states increases sharply near the conduction and valence bandedges. We find that the energy bandgap of SiGe is reduced from 0.90 to 0.83 eV as the Ge composition increases from Si0.6Ge0.4 to Si0.3Ge0.7. In contrast, similar oxide/Si1-xGex conduction-band barrier heights of similar to3.1 eV have been obtained for both SiGe cases using Fowler-Nordheim tunneling. These results are in good agreement with published theoretical and experimental data from material level characterization. The device level characterization is especially important because the SiGe composition and material property may be altered after thermal cycles for device fabrication. (C) 2004 The Electrochemical Society.
Effect of annealing temperature on physical and electrical properties of Bi3.25La0.75Ti3O12 thin films on Al2O3-buffered Si
(2002-03-18)
Sun, CL
;
Chen, SY
;
Chen, SB
;
Chin, A
;
材料科學與工程學系
The effect of annealing temperature, especially at high temperatures, on the physical and electrical properties of Bi3.25La0.75Ti3O12 (BLT) thin films on Al2O3 (10 nm)/Si has been investigated. The width of memory window in capacitance-voltage curves for BLT/Al2O3/Si capacitors annealed at temperature range of 700 degreesC-950 degreesC increases with increasing annealing temperature. At the highest annealing temperature of 950 degreesC, a large ferroelectric memory window of 13 V is obtained under +/-15 V sweep voltage, and this large ferroelectric memory window should be related to the reduced leakage current. Owing to the excellent electrical properties, the high-temperature stable BLT/Al2O3/Si capacitor is compatible with current very large scale integrated technology process. (C) 2002 American Institute of Physics.