Browsing by Author "Chung, Cheng-Ting"

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A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
Body-Tied Germanium FinFETs Directly on a Silicon Substrate
(2012-12-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Luo, Guang-Li
;
Chien, Chao-Hsin
;
電子工程學系及電子研究所
We fabricated body-tied Ge p-channel fin field-effect transistors (p-FinFETs) directly on a Si substrate with a high-kappa/metal gate stack. This scheme is fully compatible with Si standard processing. The FinFET structure has excellent control on the channel potential and thus can improve the short-channel effect. The diode with p(+)-Ge/n-Si heterojunctions illustrates a remarkably high I-ON/I-OFF > 10(6) despite the presence of misfit dislocations at the interface. The high-hole-mobility body-tied Ge p-FinFETs with a fin width W-Fin of similar to 40 nm and a mask channel length L-Mask of 120 nm depict a driving current of 22 mu A/mu m at V-G = -2 V and a low OFF-current of 3 nA/mu m at V-G = 2 V. The subthreshold characteristics with a swing of 228 mV/dec and drain-induced barrier lowering of 288 mV/V are demonstrated.
Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel
(2014-01-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Tzeng, Ju-Yuan
;
Chang, Pang-Sheng
;
Luo, Guang-Li
In this letter, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I-ON/I-OFF ratio and good short channel effect control on the channel potential. The current ratio is of similar to 6 x 10(3) (I-D) at V-DS = -0.1 V, V-GS = -3, and 0 V. The relatively low OFF-current is of 6 nA/ mu m at V-DS = -0.1 V and V-GS = 0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L-G = 120 nm.
Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation
(2014-01-01)
Chen, Che-Wei
;
Tzeng, Ju-Yuan
;
Chung, Cheng-Ting
;
Chien, Hung-Pin
;
Chien, Chao-Hsin
In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (Phi(Bp)) of 0.57 eV, resulting in a high junction current ratio of >10(4) at the applied voltage vertical bar V-a vertical bar = +/- 1 V. The nMOSFET exhibited a high I-ON/I-OFF ratio of similar to 8 x 10(3) (I-D), similar to 10(5) (I-S), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n(+)/p junction.
Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High I-ON/I-OFF Ratio Ge FinFETs
(2013-06-01)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high I-ON/I-OFF ratio (similar to 5 x 10(5), at V-D = 0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (V-TH) shift can be maintained at the level of similar to 110 mV/V and similar to 0.1 V, respectively, for Ge n-channel FinFET with L-channel = 120 nm and W-Fin = 40 nm. Multifin Ge FinFET with L-channel = 170 nm and W-Fin = 50 nm is also illustrated. Both N-and P-FinFETs possess high I-ON/I-OFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.
First Experimental Ge CMOS FinFETs Directly on SOI Substrate
(2012)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.
Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D
(2017-01-01)
Lee, Wei-Li
;
Hsu, Chung-Chun
;
Chung, Cheng-Ting
;
Lu, Yu-Hung
;
Luo, Guang-Li
We fabricated a Ge junctionless p-channel metal-oxide-semiconductor field-effect transistor (JL pMOSFET) with a raised metal source/drain (S/D) composed of a metal alloy. An ultrathin-body Ge channel was trimmed to 10 nm, which is lower than the maximum depletion width, to completely switch off the device. The fabricated Ge JL pMOSFET containing a raised Ni/NiGe S/D exhibited a high on/off current ratio (I-on/I-off) value (approximately 10(5) at V-DS =-0.1 V). The S/D series resistance of the full metal S/D structure was exactly lower than the structures of Ge/NiGe and Ge bulk S/D. Synopsys Technology Computer-Aided Design tools were used to confirm the advantages of the full metal S/D structure and demonstrate the enhancement of the S/D resistance in a device with scaled gate length. The proposed scheme is suitable for reducing the series resistance of a device with minimized dimensions. (C) 2017 The Electrochemical Society. All rights reserved.
Ge Channel MOSFETs Directly on Silicon
(2014)
Chen, Che Wei
;
Chung, Cheng-Ting
;
Chien, Chao Hsin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents high performance Ge/Si diode, trigate Ge PFET, junctionless trigate Ge PFET and strained Ge NFET directly on Si wafer. The leakage current of the Ge/Si diode is as low as <10(-7) A/cm(2). Trigate PFET depicts a driving current of 22 mu A/mu m at V-G = -2 V and a low OFF-current of 3 nA/mu m at V-G = 2 V. Junctionless trigate PFET shows I-ON/I-oFF ratio of similar to 6 x 10(4) ( I-D), similar to 6 x10(5) (I-s), and the remarkably low off-current of 450 pA/mu m at V-D = -0.1 V. Strained trigate Ge NFET is demonstrated.
Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs
(2010)
Luo, Guang-Li
;
Han, Zong-You
;
Chien, Chao-Hsin
;
Ko, Chih-Hsin
;
Wann, Clement H.
Ge films were epitaxially grown on GaAs(100) substrates and Ga(0.88)In(0.12)As(100) virtual substrates using an ultrahigh vacuum/chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n(+)-Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3246000] All rights reserved.
Germanium N and P Multifin Field-Effect Transistors With High-Performance Germanium (Ge) p(+)/n and n(+)/p Heterojunctions Formed on Si Substrate
(2013-04-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Tzeng, Ju-Yuan
;
Li, Pin-Hui
;
Chang, Pang-Sheng
We demonstrate the characteristics of p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction diodes formed by heteroepitaxial Ge grown on Si leading to high performance and very low leakage current. The ON/OFF current ratio of the p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction was >10(7) and >10(6), respectively. The OFF current density was extremely low at <10 mu A/cm(2) for the p(+)-Ge/n-Si formed with different implantation energies of 10 similar to 40 KeV and similar to 20 mu A/cm(2) for the n(+)-Ge/p-Si with different implantation energies of 20 similar to 50 KeV at a reverse bias of vertical bar V-R vertical bar = +/- 1 V, respectively. Both p and n-Ge channel multifin field-effect transistors (FinFETs) were formed by a mesa structure using these p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunctions. A high-kappa/metal gate stack was employed. The body-tied Ge multifin FinFET with a fin width (W-Fin) of similar to 40 nm, and the channel length (L-Channel) was 150 nm for p-FinFET and of 110 nm for n-FinFET, exhibiting a driving current of 174 mu A/mu m at V-G = -2 V and 102 mu A/mu m at V-G = 2 V, respectively. This is the first experimental demonstration of a body-tied high mobility Ge channel multifin FinFET using a top-down approach.
High On/Off Ratio and Very Low Leakage in p(+)/n and n(+)/p Germanium/Silicon Heterojunction Diodes
(2013-02-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Lin, Jyun-Chih
;
Luo, Guang-Li
;
Chien, Chao-Hsin
We demonstrate the characteristics of p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction diodes with a very high on/off ratio and very low leakage current using heteroepitaxial Ge grown directly on Si. The current ratio of p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction is similar to 5 x 10(7) and similar to 3 x 10(6), respectively. The remarkably low off current density is 2.1 mu A/cm(2) for p(+)-Ge/n-Si and 19 mu A/cm(2) for n(+)-Ge/p-Si at a reverse bias of vertical bar V-R vertical bar = +/- 1 V, respectively. High on current density (125 A/cm(2) for p(+)-Ge/n-Si and 54 A/cm(2) for n(+)-Ge/p-Si) with a forward bias vertical bar V-F vertical bar = +/- 1 V is obtained with a GeO2 passivation and an Al2O3 isolation. (C) 2013 The Japan Society of Applied Physics
High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain
(2014-08-01)
Chen, Che-Wei
;
Tzeng, Ju-Yuan
;
Chung, Cheng-Ting
;
Chien, Hung-Pin
;
Chien, Chao-Hsin
In this paper, we report Ge p- and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with NiGe source/drain (S/D) with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge junctions were similar to 10(5) and similar to 2 x 10(4) at vertical bar V vertical bar = +/- 1 V, respectively. Interface state densities Dit of Al2O3/GeO2/Ge stack is improved to be around 10(12)/eV(-1) cm(2) near the midgap after forming gas annealing; the gate-stack also shows excellent reliability under constant field stressing. Both p- and n-channel MOSFETs show sufficiently high ION/IOFF ratio. High driving current of similar to 9 and similar to 4 mu A/mu m at vertical bar V-GS - V-T vertical bar = +/-0.8 V and V-DS vertical bar = +/- V is obtained, respectively, for p- and n-MOSFETs. Moreover, S/D series resistance R-SD of the p- and n-MOSFET is reduced by similar to 25% and similar to 42% as compared with that of the transistors with conventional p/n junctions.
Nearly Dislocation-free Ge/Si Heterostructures by Using Nanoscale Epitaxial Growth Method
(2012-01-01)
Luo, Guang-Li
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Chung, Cheng-Ting
;
Han, Zong-You
The selective growth of germanium into nanoscale trenches on silicon substrates was investigated. These nanoscale trenches-the smallest size of which was 50 nm-were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. It was found that the formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. It was considered that for the Ge grown in nanoscale Si areas (e. g., several tens of nanometers), the TDs were readily removed during cyclic thermal annealing, predominantly because their gliding distance to the SiO2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density. (C) 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of Garry Lee
The Annihilation of Threading Dislocations in the Germanium Epitaxially Grown within the Silicon Nanoscale Trenches
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Chung, Cheng-Ting
We investigated the selective growth of germanium into nanoscale trenches on silicon substrates. These nanoscale trenches, the smallest size of which was 50 nm, were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. The formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. For the Ge grown in nanoscale Si areas (e.g., several tens of nanometers), the TDs were probably readily removed during cyclic thermal annealing predominantly because their gliding distance to the SiO(2) sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density.