Browsing by Author "Guo, Jyh-Chyurn"

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A Broadband and Scalable Lossy Substrate Model for RF Noise Simulation and Analysis in Nanoscale MOSFETs With Various Pad Structures
(2009-02-01)
Guo, Jyh-Chyurn
;
Tsai, Yi-Hsiu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An enhanced lossy substrate model is developed with important features of broadband accuracy and scalability. The broadband accuracy is justified by a good match with open pad S-parameters measured up to 110 GHz and MOSFETs' S- and Y-parameters over 40 GHz. The proven model can accurately simulate four noise parameters (NF(min), R(n), Re(Y(opt)), and Im(Y(opt))) and power spectral density of current noises (S(id) and S(ig)). The scalability has been validated over nanoscale MOSFETs with different finger numbers and adopting various pad structures (lossy, normal, and small pads). This scalable lossy substrate model attributed to two substrate RLC networks under the pads and transmission lines (TMLs) can consistently predict the abnormally strong finger number dependence and nonlinear frequency dependence of noise figure (NF(min)) revealed in devices with lossy pads. The enhanced model is useful in guiding pad and TML layouts for effective reduction of extrinsic noises and low noise design. Using a normal pad structure, the NF(min) can be effectively suppressed to approach the intrinsic performance, which is nearly independent of finger numbers.
A broadband and scalable lumped element model for fully symmetric inductors under single-ended and differentially driven operations
(2007-08-01)
Guo, Jyh-Chyurn
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Tan, Teng-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband and scalable 2-T model is developed to accurately simulate fully symmetric inductors with various dimensions. The 2-T model is defined to reflect the structure of an equivalent circuit with two identical T-model circuits. Two-step de-embedding is assisted by open and through pads for extraction of intrinsic characteristics. The accuracy is validated by 3-D fullwave electromagnetic simulation. A novel parameter extraction flow is established, and a single set of model parameters is derived to be valid for both single-ended and differentially driven topologies. The broadband accuracy is proven by a good match with S-parameters, L(omega), Re(Z(in)(omega)),and Q(omega) over frequencies up to 20 GHz. The scalability is justified by good fitting with either a linear or a parabolic function of spiral coil radii. Furthermore, all model parameters are frequency independent so as to ensure computation efficiency. This 2-T model consistently predicts the enhancement of Q(max) by 20%-30% for the symmetric inductors under a differential excitation. The Q improvement is even better than 100% over broader frequencies beyond f(m)(Q(max)).
A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities
(2007-11-01)
Guo, Jyh-Chyurn
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Tan, Teng-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband and scalable model is developed to accurately simulate on-chip inductors with various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies of up to 20 GHz, even beyond resonance. A new scheme of resistance-inductance-capacitance networks is deployed for the spiral coils and substrate to account for 3-D eddy current, substrate return path, and spiral coil to substrate coupling effects. The 3-D eddy current is identified as the key element essential to accurately simulate the broadband characteristics. Electromagnetic simulation using the Advanced Design System momentum is conducted to predict the on-chip inductor performance corresponding to a wide range of substrate resistivities (rho(Si) = 0.05 - 1 k ohm center dot cm). Three operation modes such as transverse electromagnetic mode, slow-wave mode, and eddy current mode are reproduced. The model parameters manifest themselves as physics-based through relevant correlation with psi over three operation modes. The onset of slow-wave mode can be consistently explained by a key element R-p introduced in our model, which accounts for the conductor loss due to an eddy current arising from magnetic field coupling through a substrate return path. This broadband and scalable model is useful for radio frequency circuit simulation. In addition, it can facilitate an optimum design of on-chip inductors through the physics-based model parameters relevant to varying substrate resistivities.
A compact RF CMOS modeling for accurate high-frequency noise simulation in sub-100-nm MOSFETs
(2008-09-01)
Guo, Jyh-Chyurn
;
Lin, Yi-Min
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact RF CMOS model incorporating an improved thermal noise model is developed. Short-channel effects (SCEs), substrate potential fluctuation effect, and parasitic-resistance-induced excess noises were implemented in analytical formulas to accurately simulate RF noises in sub-100-nm MOSFETs. The intrinsic noise extracted through a previously developed lossy substrate de-embedding method and calculated by the improved noise model can consistently predict gate length scaling effects. For 65- and 80-nm n-channel MOS with f(T) above 160 and 100 GHz, NF(min) at 10 GHz can be suppressed to 0.5 and 0.7 dB, respectively. Drain current noise S(id) reveals an apparently larger value for 65-nm devices than that for 80-nm devices due to SCE. On the other hand, the shorter channel helps reduce the gate current noise S(ig) attributed to smaller gate capacitances. Gate resistance R(g)-induced excess noise dominates in S(ig) near one order higher than the intrinsic gate noise that is free from R(g) for 65-nm devices. The compact RF CMOS modeling can facilitate high-frequency noise simulation accuracy in nanoscale RF CMOS circuits for low-noise design.
A Comprehensive Characterization Method for Lateral Profiling of Interface Traps and Trapped Charges in P-SONOS Cell Devices
(2017-03)
Guo, Jyh-Chyurn
;
Du, Pei-Ying
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A comprehensive characterization method has been developed in this paper for reliable lateral profiling of the interface traps (Delta N-it), localized charges (Delta N-ot), and trapped holes (Delta N-hole) in P-SONOS cell devices. Charge pumping current (I-CP) measurement can be used to probe Delta N-it and Delta N-ot from the increase of maximum I-CP (I-CP,I- max) and the shift of I-CP curve along the base level voltage (V-b). When increasing the program and erase (P/E) cycles, the negative threshold voltage (V-T) shift at both program and erase states suggests the generation of Delta N-hole. The evolution of Delta N-it, Delta N-ot, and Delta N-hole during P/E cycling can consistently explain the nonmonotonic variations of gate induced drain leakage current (I-GIDL) and substrate current (I-SUB) as well as dramatic differences between the source and drain. The lateral migration of Delta N-ot caused by extending P/E cycles may lead to the failure of two-bit operation in SONOS cell devices. The larger V-T shift and subthreshold swing, smaller read current, and lower transconductance may degrade the endurance and retention of P-SONOS when applied in Flash memory.
A New Compact Model for Accurate Simulation of RF Noise in Sub-40nm Multi-finger nMOSFETs
(2018-01-01)
Guo, Jyh-Chyurn
;
Yeh, Kuo-Liang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new compact model has been developed in this paper for accurate simulation of RF noise and extraction of actual intrinsic noise in sub-40 nm multi-finger nMOSFETs. This model can predict and verify the excess noise sources before and after deembedding, the mechanism responsible for the complicated layout dependence in various noise parameters, and facilitate optimization design for low noise devices and circuits in nanoscale CMOS technology.
A new lossy substrate model for accurate RF CMOS noise extraction and simulation with frequency and bias dependence
(2006-11-01)
Guo, Jyh-Chyurn
;
Lin, Yi-Min
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f(T) n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I-d, g(m), Y-parameters, and f(T) under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NFmin as low as 0.6-0.7 d at 10 GHz indicates the advantages of super-100 GHz f(T) offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R-n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology.
A New Method for Accurate Extraction of Source Resistance and Effective Mobility in Nanoscale Multifinger nMOSFETs
(2015-09-01)
Guo, Jyh-Chyurn
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Lo, Yi-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new method is is developed for accurate extraction of the effective mobility (mu(eff)) in the multifinger nMOSFETs with various poly-to-poly (PO-PO) spaces. The wide PO-PO space intends to increase the tensile stress from a contact etching stop layer (CESL) and yields higher mu(eff) in the nMOSFETs. However, the source resistance (RS) emerges as a critical parasitic element in the multifinger devices with a large finger number. The wide PO-PO space generally leads to the further increase of RS, which may offset mu(eff) improvement and degrade transconductance (gm). A two-end source line is proposed to reduce RS and the impact on gm. The complicated layout-dependent effects containing the CESL strain, RS, and 3-D fringing capacitances bring a crucial challenge to the mu(eff) extraction. In this paper, a distributed transmission line model is derived for a reliable determination of RS, which is a key to the realization of accurate extraction of mu(eff) and layout-dependent effects in multifinger devices.
A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs
(2011-09-01)
Yeh, Kuo-Liang
;
Guo, Jyh-Chyurn
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Q(inv) and effective mobility mu(eff) has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., C(of) and C(f(poly-end)), respectively. Both categories of parasitic capacitance lead to overestimated Q(inv) and underestimated mu(eff). The increase in effective channel width W(eff) due to Delta W from shallow trench isolation (STI) top-corner rounding may compensate mu(eff) degradation due to STI stress. The tradeoff between mu(eff) and W(eff) determines the impact of width scaling on I(DS) and G(m). A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of mu(eff) in multifinger MOSFETs with various layouts and narrow widths down to 0.125 mu m.
A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs
(2009-08-01)
Guo, Jyh-Chyurn
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Yeh, Chih-Ting
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance C(of) dominates around 25% of the intrinsic gate capacitance (C(gint)) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C(of)/C(gint) above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.
A simple analytical model to accurately predict self-resonance frequencies of on-silicon-chip inductors in TEM mode and eddy current mode
(2008-08-01)
Guo, Jyh-Chyurn
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Tan, Teng-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For the first time, a simple analytical model in the form of explicit formulas was derived for on-silicon-chip inductors. This analytical model can accurately calculate self-resonance frequencies (f(SR)) in TEM mode and eddy current mode corresponding to very high and very low substrate resistivities (rho(Si)). Furthermore, this derived model can predict and explain the interesting result that f(SR) keeps nearly a constant independent of rho(Si) in TEM and eddy current modes but is critically determined by the inductance and parasitic capacitances. The simple model is useful in on-silicon-chip inductor design for increasing f(SR) under specified inductance target for broadband RF circuit design and applications. (C) 2008 Elsevier Ltd. All rights reserved.
Analytical Modeling of Proximity and Skin Effects for Millimeter-Wave Inductors Simulation and Design in Nano Si CMOS
(2014-01-01)
Chan, Ren -Jia
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Analytical models of proximity and skin effects have been developed in this paper to calculate and predict the frequency dependent resistance, Re(Z(m)) and quality factor, Q for mm-wave inductor design. The derived models incorporate layout and material parameters, and frequency in an explicit form suitable for circuit simulation. The accuracy has been proven by a close match with Re(Z(in)) and Q measured from mm-wave inductor (L(dc similar to)150pH, Q(max)similar to 17, f(SR)>> 65GHz) fabricated by 65nm CMOS process with 0.9 mu m standard top metal.
Flicker Noise in Nanoscale pMOSFETs with Mobility Enhancement Engineering and Dynamic Body Biases
(2009)
Yeh, Kuo-Liang
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Ku, Chih-You
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Hong, Wei-Lun
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
The uni-axial compressive strain from e-SiGe S/D combined with dynamic body biases effect on flicker noise of pMOSFETs is presented in this paper. This compressive strain contributes higher mobility but the worse flicker noise in terms of higher S(ID)/I(D)(2) becomes a potential killer to RF/analog circuits. Forward body biases (FBB) can reduce the flicker noise but the degraded body bias effect in strained pMOSFETs makes it not as efficient as the standard ones without strain. Hooge's mobility fluctuation model is adopted to explain the uni-axial strain and dynamic body biases effect on flicker noise. The increase of Hooge parameter alpha(H) is identified the key factor responsible the degraded flicker noise in strained pMOSFETs.
Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs
(2011-09-01)
Yeh, Kuo-Liang
;
Guo, Jyh-Chyurn
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of MOSFET layout-dependent stress on high-frequency performance and flicker noise has been investigated. The proposed donut MOSFETs demonstrate the advantages over the standard multifinger MOSFETs, such as the lower flicker noise S(ID)/I(DS)(2) in the low-frequency domain and the higher cutoff frequency f(T) in the very high-frequency region. The elimination of the transverse stress sigma(perpendicular to) from shallow trench isolation (STI) and the suppression of interface traps along the STI edge are proposed as the primary factors responsible for the enhancement of the effective mobility mu(eff), as well as f(T), and the reduction of flicker noise. The significantly lower flicker noise realized by donut devices suggests the reduction of STI-generated traps and the suppression of mobility fluctuation due to eliminated transverse stress. The former is applied to n-channel MOS in which the flicker noise is determined by the number-fluctuation model. The latter is responsible for p-channel MOS whose flicker noise is dominated by the mobility-fluctuation model.
Low Frequency Noise in Nanoscale pMOSFETs with Strain Induced Mobility Enhancement and Dynamic Body Biases
(2009)
Yeh, Kuo-Liang
;
Ku, Chih-You
;
Hong, Wei-Lun
;
Guo, Jyh-Chyurn
;
電子工程學系及電子研究所
Local strain effect on low frequency noise (LFN) of pMOSFETs with gate length down to 60 nm was investigated in this paper. Novel and interesting results were identified from the pMOSFETs adopting embedded SiGe (e-SiGe) in source/drain for uni-axial compressive stress. This local compressive strain can realize significant mobility enhancement and desired current boost in nanoscale pMOSFETs. However, the dramatic increase of LFN emerges as a penalty traded off with mobility enhancement. The escalated LFN may become a critical killer to analog and RF circuits. Forward body biases (FBB) can improve the effective mobility (mu(eff)) and reduce LFN attributed to reduced normal field (E(eff)). However, the benefit from FBB becomes insignificant in strained pMOSFETs with sub-100 nm gate length.
Low Power UWB CMOS LNA Using Resistive Feedback and Current-Reused Techniques Under Forward Body Bias
(2017-01-01)
Guo, Jyh-Chyurn
;
Lin, Ching-Shiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A ultra-wideband (UWB) low noise amplifier (LNA) has been realized in 0.18 mu m CMOS technology. The current-reused method combined with forward body bias (FBB) in a cascade amplifier can enable an aggressive voltages scaling, such as V-DD and V-G1 to 1.0V and 0.53V, i.e. 44.5% and 70.6% reduction compared to the typical VDD of 1.8V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The on-chip measurement indicates power gain (S-21) of 10.55 similar to 12.6dB and noise figure (NF50) of 3.2 similar to 3.95 dB through the UWB (3 similar to 10.5GHz). This UWB LNA with small chip area (0.69mm(2)) provides a solution for low voltages, low power, and low cost.
Low Voltage and Low power UWB CMOS LNA using Current-Reused and Forward Body Biasing Techniques
(2017-01-01)
Guo, Jyh-Chyurn
;
Lin, Ching-Shiang
;
Liang, Yu-Tang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated in 0.18 mu m CMOS technology. The successful integration of current-reused and forward body biasing (FBB) techniques in a cascade amplifier can enable an aggressive scaling of the supply voltages, V-DD and V-G1 to 1.0V and 0.53V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The measured power gain (S-21) can reach 10.55 similar to 12.6dB and noise figure (NF50) is 3.2 similar to 3.95 dB through the UWB (3 similar to 10.5GHz). This UWB LNA with small chip area (0.69mm(2)) provides a solution of low voltages, low power, and low cost.
Low-K/Cu CMOS-based SoC technology with 115-GHz f(T), 100-GHz f(max), noise 80-nm RF CMOS, high-Q MiM capacitor, and spiral Cu inductor
(2006-08-01)
Guo, Jyh-Chyurn
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Logic CMOS-based RF technology is introduced for a 10-Gb transceiver in which active and passive RF devices have been realized in a single chip. RF nMOS of 115-GHz f(T), 100-GHz f(max), and sub-1.0-dB NFmin at 10 GHz have been fabricated by aggressive device scaling and layout optimization. High-Q MiM capacitor and spiral Cu inductors have been successfully implemented in the same chip by 0.13-mu m low-K/Cu back end of integration line technology. Core 1.0 V MOS and/or junction varactors for VCO at 10 GHz are offerings free of extra cost and realized by the elaborated layout.
Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs
(2013-01-01)
Yeh, Kuo-Liang
;
Guo, Jyh-Chyurn
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of narrow-width effects on high-frequency performance like f(T), f(MAX), and RF noise parameters, such as NFmin and R-n, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower R-g and higher f(MAX). However, these narrow-OD devices suffer f(T) degradation and higher NFmin, even with the advantage of lower R-g. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.
New Observation and Analysis of Layout Dependent Effects in Sub-40nm Multi-Ring and Multi-Finger nMOSFETs for High Frequency Applications
(2019-01-01)
Li, Zu-Cheng
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Guo, Jyh-Chyurn
;
Lin, Jinq-Min
;
交大名義發表
;
National Chiao Tung University
Multi-finger (MF) and multi-ring (MR) nMOSFETs were designed and fabricated in 40nm CMOS technology to explore the layout dependent effects in key device parameters and parasitic RC responsible for RF performance. For the first time, the experimental proves the advantages of MR nMOSFETs, such as the increase of effective mobility (mu(eff)), transconductance (g(m)), and channel current (I-DS), and smaller parasitic source resistance (R-S), all of which are in favor of higher speed and higher frequency. However, the undesired increase of 3-D fringing capacitances may bring a critical trade-off influencing high frequency performance. In this paper, new observation and in-depth analysis of the complicated layout dependent effects can facilitate the device layout optimization in the right direction for RF and mm-wave design and applications.