Browsing by Author "Hu, Robert"

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33 similar to 50GHz CMOS Receiver with Wideband RF, IF and LO Chain
(2017-01-01)
Huang, Ching-Ying
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Wu, Kung-Long
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Hu, Robert
;
Chang, Chi-Yang
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電子工程學系及電子研究所
This manuscript describes the Q-band 90nmCMOS receiver design where the 33 similar to 50GHz RF-LNA, actively-biased double-balanced mixer, 10GHz IF amplifier, wideband frequency tripler and power amplifier in the LO chain are all integrated into one single chip. With overall power consumption of 170mW under 1.2V bias, the measured conversion gain is 15dB, noise figure close to 8dB, inputreferred P1dB around -30dBm, and the LO-IF port isolation is more than 60dB. Therefore, it can be easily driven by an external 11 similar to 16GHz signal source and used in applications such as next-generation broadband mobile communications where several specific Q-band frequency points have been considered. However, contrary to most receiver designs where the optimization is carried out over a relatively narrow bandwidth, here the main challenge lies in how to effectively extend the RF, IF, and LO bandwidth simultaneously without rendering performance deterioration. By possessing such broadband RF, IF, and LO characteristics, this Q-band circuit is also eligible for use in radio-astronomical, atmospheric, and other scientific instrumentations.
40 nm-CMOS W-band Phase Shifter for Millimeter-wave Phased Array
(2019-01-01)
Huang, Ching-Ying
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Hsieh, Kuan-Han
;
Hu, Robert
;
電機學院
;
College of Electrical and Computer Engineering
With its low attenuation and high directivity, the 77 similar to 110 GHz (W-band) frequency range is suitable for long-distance broadband applications. Although only 77 GHz and 94 GHz have been used for vehicular radar and military surveillance so far, the W-band spectra is destined to play an even important role in the post-5G era. This manuscript describes our development on the 40 nm-CMOS W-band phase shifter design where 5 bits are used for phase shift of 11.25 degrees while additional 4-bit logics are for fine-tuning purpose. The input signal is first be amplified by a wideband amplifier and then transformed through poly-phase circuit into I/Q signals, whose magnitude will then be altered by the following digital VGAs. By making the vector sum at the output, phase shifting in the range of 0 degrees similar to 360 degrees can be obtained and the resolution is 11.25 degrees.
77-110 GHz 65-nm CMOS Power Amplifier Design
(2014-05-01)
Wu, Kun-Long
;
Lai, Kuan-Ting
;
Hu, Robert
;
Jou, Christina F.
;
Niu, Dow-Chih
This paper details the development of our millimeter-wave wideband power amplifier design. By treating the power combiner as an impedance transformer which allows different loading impedance to be taken into account, a compact wideband power-combining network can be constructed. With small transmission-line attenuation being sustained and maximum output power easily extracted from the transistors over the 77-110 GHz frequency range, a power amplifier can then be designed using 65-nm CMOS process to cover the whole W-band. In the on-wafer measurement, the gain is around 18 dB, the output reflection coefficients is below -10 dB, and the output-referred 1 dB compression point can reach 12 dBm at 1.2 V bias condition; when the bias is increased to 2.5 V, a 18 dBm output power is recorded. To our knowledge, this is the first CMOS power amplifier that covers the whole W-band.
77-110GHz 90nm-CMOS Receiver Design
(2013)
Yu, Jo-Han (Judy)
;
Liao, Chien-Hsiung
;
Hsieh, Cheng-Huang
;
Hu, Robert
;
Niu, Dow-Chih
This manuscript details our latest 90nm CMOS W-band receiver design where the RF LNA, resistive mixer, IF differential amplifier and LO tripler have been integrated, thus allows the whole 77-110GHz spectrum to be down-converted into quasi-DC-33GHz using a much lower microwave frequency. In addition to being used in our broadband receiver array project, this W-band circuit is also eligible for the conventional 77/94GHz vehicular and surveillance applications. This 90nm-CMOS receiver with LO tripler has around -0.4dB conversion gain, 18dB noise figure, 48dB LO-IF isolation, and its chip size is 950-times-750um(2), with 114mW power dissipation at 1.3V DC bias.
77GHz Power Amplifier Design Using WIN 0.1 mu m GaAs pHEMT Process
(2014-01-01)
Lai, Kuan-Ting
;
Wu, Kun-Long
;
Hu, Robert
;
Jou, Christina F.
;
交大名義發表
This paper reports our 77GHz power-amplifier designs using WIN 0.1 mu m GaAs pHEMT process provided by the commercial WIN foundry. The first two stages of the power amplifier is made of common-source transistors for gain amplification, and then followed by two-and four-paralleled transistors where the 3dB two-way Wilkinson power splitters/combiners for large output power delivery are used. All the by-pass capacitors for drain and gate biases have been optimized to have small series impedance at W-band. The input DC-blocking capacitor is made coupled lines, which also functions as tuning circuit. With 2.5V and 350mA drain bias, the small-signal gain is 12dB, as measured on-wafer at room temperature; the output-referred 1dB compression point is 6dBm. With 3dBm input power, the saturated output power is around 8.6dBm. Good input- and output-port matching has also been observed. The chip size is 1000x2500 mu m(2) and it consumes 875mW.
A 34-42GHz Single-Side-Band Transmitter with Switchable VCO/PLL in 90nm-CMOS Process
(2017-01-01)
Huang, Ching-Ying
;
Wu, Kun-Long
;
Hu, Robert
;
Chang, Chi-Yang
;
電子工程學系及電子研究所
This manuscript describes a 34-42GHz single-sideband 90nm-CMOS transmitter where PLL has been integrated into the LO chain and, with I/Q input and two-stage up-conversion, a 30dB image-rejection ratio is achieved within the intended bandwidth. This transmitter's wideband tuning range is made possible by the use of additional capacitor on the VCO, and the phase noise of the resulting RF output is in the range of -70 to -90dBc/Hz at 1MHz, and all below 100dBc/Hz at 10MHz. The circuit's IF-to-RF conversion gain is 30dB, with saturated output power around 5dBm, and the total power consumption is 260mW. Through the control of the power amplifier's drain bias, a 50dB power level difference can be obtained, thus allows signal modulation and further combination with the receiver. This 1100x650um(2) transmitter can be used as a prototypical circuit to explore next-generation mobile communication and civilian radar array systems.
A 78 similar to 102 GHz Front-End Receiver in 90 nm CMOS Technology
(2011-09-01)
Su, Hsuan-Yi
;
Hu, Robert
;
Wu, Chung-Yu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, a 78 similar to 102 GHz front-end receiver designed in 90 nm CMOS technology is presented. It consists of an ultra-wideband low-noise amplifier, a subharmonic mixer, and an IF buffer. This receiver has a peak gain of 11.8 dB at 94 GHz with the noise figure of 13.4 dB. The measured input-referred 1 dB compression point is -14.5 dBm and the total power dissipation is 18.6 mW. The chip size is 680 x 1020 mu m(2).
A DC-20GHz CMOS Active Power Divider Design
(2010-01-01)
Huang, Jing-Ying
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Wu, Hui-I
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Hu, Robert
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Jou, Christina F.
;
Niu, Dow-Chi
We report the design of a wideband active power divider using commercial CMOS process. This circuit is made of two distributed amplifiers sharing a common input artificial transmission line while two distinct transmission lines are employed for the output ports. Since the input transmission line tends to be overly capacitive now when compared with the conventional distributed amplifier, the constituting gain cells need to be revised so as to retain the intended 20GHz bandwidth. Small input and output reflection coefficients have been observed, and the measured output port isolation is below -30dB across the whole bandwidth, which is beyond the reach of passive power dividers. Magnitude and phase imbalances of the two output ports are 0.2dB and 0.4 degrees at 15GHz and 0.9dB and 0.6 degrees at 20GHz. The noise figure is 6.9dB at 15GHz and 9.4dB at 20GHz. The input-referred 1dB compression point is -9.5dBm at 15GHz and -10.5dBm at 20GHz. With the bias of 2.5Volt and 64Amp, the total power dissipation is 160mWatt.
An analytical approach on the determination of generator reflection coefficients used in the noise-parameter measurement
(2006-01-01)
Hu, Robert
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Sang, Tzu-Hsien
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In performing microwave and millimeter-wave noise-parameter measurements, a set of generator reflection coefficients and their corresponding noise temperatures need to be measured first. Allowing measurement errors, values of these generator reflection coefficients will affect the accuracy of final results. Though simulation alone can be used to find out on the Smith chart the preferred pattern of the generator reflection coefficients, its analytical counterpart has not been explored yet. This paper intends to derive the related mathematical expressions, thus complements and strengthens the simulation method.
An experimental investigation of air cooling thermal module using various enhancements at low Reynolds number region
(2010-12-01)
Yang, Kai-Shing
;
Li, Shu-Lin
;
Chen, Ing Youn
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Chien, Kuo-Hsiang
;
Hu, Robert
This study examines the airside performance of heat sinks having fin patterns of plate fin (Type I), interrupted fill geometry (Type II), dense vortex generator (Type III), and loose vortex generator (Type IV). Test results indicate that the heat transfer performance is strongly related to the arrangement of enhancements. The interrupted and dense vortex generator configurations normally contribute more pressure drop penalty than improvements of heat transfer. This is especially pronounced when operated at a lower frontal velocity. Actually the plain fin geometry outperforms most of the enhanced fin patterns such as of Type II and Type Ill at the fully developed region. This is because a close spacing prevents the formation of vortex, and the presence of interrupted surface may also suffer from the degradation by constriction of conduction path. The results suggest that the vortex generators operated at a higher frontal velocity is more beneficial than that of plain fin geometry. In association with the VG-1 criteria (same pumping power and same heat transfer capacity), the results show that effective reduction of surface area can be achieved when the frontal velocities are at 3-5 m s(-1) and the fin patterns are triangular, triangular attack, or two-groups dimple. The result from the present experiment suggests that the asymmetric combination such as using loose vortex generator (Type IV) can be quite effective. The triangular attack vortex generator is regarded as the optimum enhancement design for it could reduce 12-15% surface area at a frontal velocity around 3-5 m s(-1). The asymmetric design is still applicable even when the fin pitch is reduced to 1 mm. (C) 2010 Elsevier Ltd. All rights reserved.
Analysis and design of wideband active power splitter with interleaf transmission line topology
(2019-11-01)
Huang, Ching-Ying
;
Hu, Robert
;
Niu, Dow-Chi
;
Chang, Chi-Yang
;
電機學院
This article proposes a new wideband active power splitter design where the gain cells along the input transmission line are arranged in interleaf rather than the conventional parallel style, thus the circuit's high-frequency performance can be greatly improved. Both theoretical analysis and circuit simulation have been carried out; as a demonstration, parallel and interleaf active power splitters are designed using 0.1 mu m GaAs pseudo-morphic heterostructure field effect transistors (GaAs pHEMT) process and measured on-wafer. The results clearly indicate the superiority of the interleaf topology. A 40 GHz interleaf active power splitter in 90 nm complementary metal-oxide-semiconductor (CMOS) is then presented where the magnitude and phase imbalance between the two output ports are 0.15 dB and 2.6 degrees at 20 GHz, and 0.16 dB and 14 degrees at 40 GHz. The output-port isolation is better than 30 dB across the whole frequency range.
Analysis of wide-IF-band 65 nm-CMOS mixer for 77-110 GHz radio-astronomical receiver design
(2019-05-01)
Huang, Ching-Ying
;
Wu, Kun-Long
;
Hu, Robert
;
Chang, Chi-Yang
;
電子工程學系及電子研究所
This manuscript presents the design of a W-band receiver in which an radio frequency-low noise amplifier (RF-LNA), a wideband mixer, intermediate frequency (IF) amplification, a local oscillator frequency (LO) tripler and a driving amplifier are all integrated into one single chip of 1050 x 820 mu m(2). To effectively extend the mixer's IF bandwidth while retaining its conversion gain, impacts of the mixing transistor's drain bias and output loading impedance are explored using a dual-modulation conversion-matrix method, which allows both the LO-induced transconductance modulation and channel-conductance modulation to be considered simultaneously. It is shown that, by merging the input capacitance of the IF amplifier into a high-impedance artificial transmission line, an actively biased mixer can have constant conversion gain over broad bandwidth. A 77-110 GHz 65 nm-complementary metal-oxide-semiconductor (CMOS) receiver with 33 GHz IF bandwidth is then designed and measured. Its conversion gain and noise figure are 10 and 20 dB, respectively, and the input-referred P1 dB is -15 dBm; the overall power consumption is 330 mW under 1.3 V drain bias.
Complementary UWB LNA Design Using Asymmetrical Inductive Source Degeneration
(2010-07-01)
Wu, Hui-I
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Hu, Robert
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Jou, Christina F.
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電信工程研究所
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Institute of Communications Engineering
This letter proposes a novel LNA design method where the complementary transistor topology is combined with asymmetrical inductive source degeneration to achieve matched input impedance over a wide bandwidth. A 2-10 GHz LNA is designed and fabricated using a commercial 0.18 mu m RF-CMOS process to verify the feasibility of our proposed method. In the intended bandwidth, this LNA has matched input impedance, 20 dB power gain, and 2.4-3.4 dB noise figure, with 25.65 mW power consumption.
Cryogenic analog-to-digital converters using spread spectrum technology for coherent receivers
(2012-01-01)
Shiao, Yu-Shao Jerry
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Chiueh, Tzihong
;
Hu, Robert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We propose analog-to-digital converters (ADCs) using spread spectrum technology in cryogenic receivers or at warm room temperature for coherent receiver backend systems. As receiver signals are processed and stored digitally, ADCs play a critical role in backend read-out systems. To minimize signal distortion, the down-converted signals should be digitized without further transportation. However, digitizing the signals in or near receivers may cause radio frequency interference. We suggest that spread spectrum technology can reduce the interference significantly. Moreover, cryogenic ADCs at regulated temperature in receiver dewars may also increase the bandwidth usage and simplify the backend digital signal process with fewer temperature-dependant components. While industrial semiconductor technology continuously reduces transistor power consumption, low power high speed cryogenic ADCs may become a better solution for coherent receivers. To examine the performance of cooled ADCs, first, we design 4 bit 65 nm and 40 nm CMOS ADCs specifically at 10 K temperature, which commonly is the second stage temperature in dewars. While the development of 65 nm and 40 nm CMOS ADCs are still on-going, we estimate the ENOB is 2.4 at 10 GSPS, corresponding to the correlation efficiency, 0.87. The power consumption is less than 20 mW.
DC-40GHz Wideband Active Power Splitter Design with Interleaved Transmission-Line Gain Cells
(2015)
Huang, Ching-Ying
;
Hu, Robert
;
電機學院
;
電子工程學系及電子研究所
;
College of Electrical and Computer Engineering
This paper proposes the wideband active power splitter design where the gain cells are arranged in interleaf rather than the conventional parallel style. By reducing the shunt capacitance of the input transmission line, thus extending its bandwidth, the circuit\'s high-frequency performance can be greatly improved. A DC-40GHz interleaf active power splitter is then designed using 90nm-CMOS process. With 5dB gain, the magnitude and phase imbalance between the two output ports are 0.15dB and 2.6 degrees at 20GHz, and 0.16dB and 14 degrees at 40GHz. The output-port isolation S-23 is mostly below -30dB.
DC-50GHz Wideband Phase-Compensated 90nm-CMOS Active Balun Design
(2015)
Wu, Kun-Long
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Lai, Kuan-Ting
;
Hu, Robert
;
Chang, Chi-Yang
;
電機學院
This manuscript explores the output phase imbalance observed in the common-gate common-source transistors, and gives a mathematical formulation in determining the length of the compensation transmission line. To demonstrate the validity of this wideband phase-compensation technique, a DC-50GHz active balun is designed using commercial 90nm-CMOS process and then measured, where the phase imbalance is less than 5 degrees while the magnitude imbalance is within 1dB. All ports are well-matched and positive gain has been sustained up to 50GHz; the output-referred 1dB compression point is around 3dBm. With 3V and 32.5mA drain bias, the total power consumption is 97.5mW. To our knowledge, this is the widest active balun ever designed with such tight output phase requirement.
Design of 18 similar to 26GHz Receiver with Wideband RF, LO and IF in 0.15 mu m GaAs pHEMT Process
(2017-01-01)
Chen, Ying
;
Yu, Zhong-I
;
Huang, Ching-Ying
;
Hsieh, Kuan-Han
;
Hu, Robert
This paper describes our progress in designing the K-band receiver in WIN 0.15 mu m GaAs pHEMT process. The LNA contains three stages of common-source transistors, and its noise performance has been optimized over the intended bandwidth; the following mixer is made of single-balanced transistors where the edge-coupled Marchand balun provides the required 18 similar to 26GHz differential-mode LO while active balun is used for combining the 8GHz IF signals. The conversion gain measured on-wafer at room temperature is around 20dB and the noise temperature is close to 300K, with overall power consumption 140mW, and the chip area is 1000x2500 mu m(2.) A close inspection on the wide-IF-band noise measurement procedure is also provided where the impact of conversion gain on the measured T-n is explored. This receiver circuit will facilitate the construction of large focal plane arrays where compact cryogenic receiver module is in urgent demand.
Design of Wide-IF-Band CMOS Mixer with LO Multiplier
(2013)
Tsai, Han-Ting
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Tseng, Pei-Ling
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Chang, Che-Wei
;
Hu, Robert
;
Jou, Christina F.
This paper reports the development of K-band wide-IF-band CMOS mixer with LO multiplier suitable for wideband applications. To achieve such broad bandwidth, several design techniques-such as current-reuse differential-pair with LC resonance circuit, and simultaneous in-band gain peaking and off-band gain tailoring-have been analyzed and employed. The on-wafer measurement of this 17.4-26.1GHz TSMC 0.18 mu m CMOS mixer with LO doubler shows a -1dB conversion gain, 11dB noise figure, -6dBm input-referred 1dB compression point, 40dB RF-IF isolation, and 45dB LO-IF isolation at 8.7GHz. The chip size is 1400 x 1300 mu m(2).
IL analysis for 8-way power combining network in 77-110 GHz 40 nm-complementary metal-oxide-semiconductor PA design
(2019-11-01)
Huang, Ching-Ying
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Wu, Pin-Hsuan
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Wu, Kun-Long
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Hu, Robert
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Chang, Chi-Yang
In this study, the authors will investigate the insertion loss (IL) of the broadband 8-way power combiner used in their millimetre-wave power amplifier (PA) design. By treating this combiner as impedance transformer under resistor-capacitor (RC)-loading condition, both the characteristic impedance and electrical length of the constituting metal lines can be obtained, where the much shorter line length suggests wider bandwidth and lower IL. However, proper loss analysis must take into account the multi-reflection of voltage wave along these mismatched transmission lines, i.e. the use of the power attenuation expression ${\rm e}<^>{ - 2\alpha L}$e-2 alpha L is just not accurate enough. With their derived equations, it shows that the IL of their proposed 8-way combiner can be as low as 0.92 dB at 94 GHz, which is much smaller than the 1.5 dB for the conventional quarter-wavelength combiner. Mathematics for the IL of the drain-bias shunt stub and the output DC-blocking capacitor has also been derived. As a demonstration, a 77-110 GHz 40 nm-complementary metal-oxide-semiconductor PA made of cascode transistors is then designed that has more than 18 dB gain, and its OP1 dB is around 13 dBm across the whole frequency range.
Microwave and Millimeter-Wave CMOS Frequency Doubler and Tripler Designs
(2014-01-01)
Wu, Kun-Long
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Tsai, Han-Ting
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Tseng, Pei-Ling
;
Hu, Robert
;
Jou, Christina F.
This manuscript describes our 17.4GHz 0.18 mu m-CMOS doubler and 77GHz 65nm-CMOS tripler designs. For the doubler, attention has been made on effectively suppressing the fundamental, third and forth harmonics using LLC filtering networks and balun. As for the tripler, the unwanted second-order harmonic can be suppressed through the use of large source impedance on the differential pair while the fundamental signal leakage is removed by an embedded notch filter; therefore, the intended third-harmonic output is almost 40dB larger than all the other spurious signals. The tripler chip size is 700x940um, and it consumes 93mW under 1.2V bias; the 3dB bandwidth for output is 9GHz.