Browsing by Author "Lee, Yao-Jen"

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1/f noise in micrometer-sized ultrathin indium tin oxide films
(2013-09-16)
Yeh, Sheng-Shiuan
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Hsu, Wei-Ming
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Lee, Jui-Kan
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Lee, Yao-Jen
;
Lin, Juhn-Jong
We have measured the low-frequency noises of ultrathin indium tin oxide films to investigate the effect of post annealing on the noise level. The noises obtained obey an approximate 1/f law in the frequency range f approximate to 0.1-20 Hz. The microstructures and grain sizes of our films were altered by adjusting the annealing conditions. An enhancement of the noise level was observed for those samples comprising smaller grains, where numerous grain boundaries exist. This enhancement in the noise level is ascribed to atomic diffusion along grain boundaries or dynamics of two-level systems near the grain boundaries. (C) 2013 AIP Publishing LLC.
32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction
(2016-05)
Hou, Fu-Ju
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Sung, Po-Jung
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Hsueh, Fu-Kuo
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Wu, Chien-Ting
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Lee, Yao-Jen
Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 mu A/mu m, a large current ON/OFF ratio of > 5 x 10(7), and minimal short-channel effect using V-G = 2 V and V-D = 1 V.
3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
;
Lu, Yu-Lun
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Hsueh, Fu-Kuo
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Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
3D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating Current
(2013-01-01)
Hsu, Chung-Wei
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Wan, Chia-Chen
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Wang, I-Ting
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Chen, Mei-Chin
;
Lo, Chun-Li
The 3D double-layer vertical RRAM with ultralow sub-mu A operating current and high self-rectifying ratio over 10(3) has been demonstrated for the first time. This Ta/TaOx/TiO2/Ti interfacial switching device overcomes the intrinsic trade-off between operating current and variability in filamentary RRAMs and shows promising potential for high-density data storage.
A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO(2)/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
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Lee, Yao-Jen
;
Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO(2)/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO(2)/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
;
Lee, Yao-Jen
;
Lin, Horng-Chih
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Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
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Huang, Shih-Chiang
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Chung, Cheng-Ting
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Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing
(2011-07-01)
Hsueh, Fu-Kuo
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Lee, Yao-Jen
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Lin, Kun-Lin
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Current, Michael I.
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Wu, Ching-Yi
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 x 10(15) ion/cm(2), were annealed by microwave methods at temperatures below 500 degrees.C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross-sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.
Atomic layer defect-free etching for germanium using HBr neutral beam
(2019-09-01)
Fujii, Takuya
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Ohori, Daisuke
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Noda, Shuichi
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Tanimoto, Yosuke
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Sato, Daisuke
The authors developed extremely selective etching for making an atomically flat, defect-free germanium fin (Ge Fin) structure. The etching uses a hydrogen bromide (HBr) neutral beam (NB), and they investigated the etching reaction differences between the HBr NB and a Cl-2 NB. No sidewall etching by HBr NB occurred at 90 degrees C, although that by Cl-2 NB occurred at more than 90 degrees C. This was due to the different boiling points of GeBr4 and GeCl4 as the reacted layer was formed by NB irradiation on the Ge surface. As a result, the Ge sidewall etching by Cl-2 NB occurred above 90 degrees C, whereas that by HBr NB did not occur at 90 degrees C. Additionally, nonvolatile bromide protected layers, such as GeBr4 and SiBrxOy, were deposited on the Ge sidewall and the SiO2 top surface in case of using HBr, respectively. Then, the authors succeeded in fabricating the atomically flat, defect-free Ge Fin structure with the extremely selective HBr NB etching. This result shows that HBr NB can more precisely achieve sub-10-nm scale atomic layer Ge etching for 3D Fin-type MOSFETs.
Atomic layer germanium etching for 3D Fin-FET using chlorine neutral beam
(2019-03-01)
Ohori, Daisuke
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Fujii, Takuya
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Noda, Shuichi
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Mizubayashi, Wataru
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Endo, Kazuhiko
In case of using pure chlorine chemistry, Ge etching reactivity is three times higher than Si etching reactivity because of the larger lattice spacing in Ge. As a result, during the chlorine plasma etching of a Ge Fin structure, there are serious problems such as a large side-etching and large surface roughness on the Ge sidewall. Conversely, the authors found that several-ten nanometer-width Ge Fin structures with defect-free, vertical, and smooth sidewalls were successively delineated by chlorine neutral beam etching. Based on these results, the problems caused by chlorine plasma etching are considered to be due to the enhancement of chemical reactivity caused by defect on the sidewall with the irradiation of ultraviolet/vacuum ultra violet (UV/VUV) photons. Namely, it is clarified that the neutral beam etching could achieve real atomic layer etching by controlling the defect without any UV/VUV photons on the sidewall surface for future nanoscale Ge Fin structures. Published by the AVS.
Boosting Ge-epi N-well Mobility with Sn Implantation and P-well Mobility with Cluster-C Implantation
(2018-01-01)
Borland, John
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Chaung, Shang-Shiun
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Tseng, Tseung-Yuen
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Lee, Yao-Jen
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Joshi, Abhijeet
We investigated the effects of Sn, Si and cluster-C implantation into both P-well and N-well doped regions of 100nm Ge-epilayer on Si wafers after RTA annealing. For the P-well case a 7.3x increase in Hall bulk mobility to 3384cm(2)/Vs with cluster-C implant and for the N-well case a 4.6x increase in Hall bulk mobility to 2062cm(2)/Vs with Sn implant. Measuring layer mobility depth profiles shows mobility in the top 10-20nm of the surface can be up to 6000cm(2)/Vs for N-well with Sn implant and >10,000cm(2)/Vs for P-well with Sn implant.
Boosting Ge-epi P-well Mobility & Crystal Quality with Si or Sn Implantation and Melt Annealing
(2018-01-01)
Borland, John
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Chaung, Shang-Shuin
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Tseng, Tseung-Yuen
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Joshi, Abhij Eet
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Basol, Bulent
We investigated the effects of Si, Sn and cluster-C implantation into both P-well and N-well doped regions of Ge-epi on Si wafers after laser annealing. XRD analysis shows improved Ge-epi crystallinity after >1.5J/cm(2) laser melt annealing (liquid phase epitaxial regrowth) compared to sub-melt annealing (solid phase epitaxial regrowth). For the P-well case the Ge-epi Rs decreased to 1,600 Omega/square compared to Si at 3,400 Omega/square suggesting a hole mobility increase of 2.1x from 150cm(2)/V-s to 315cm(2)/V-s but actual measured Hall mobility was 650cm(2)/V-s to a depth of 60nm, an increase of 4.3x. The 1.8J/cm(2) laser melt anneal with Si implant improved mobility uniformly to 700cm(2)/V-s to a depth of 100nm while Sn implant improved mobility to 900cm(2)/V-s from the Ge-epi surface to a depth of 70nm then increases to 3000cm(2)/V-s at a depth of 100nm. Measuring mobility depth profiles can be very critical in engineering surface and bulk mobility improvements which can be determined by chemical compositional changes in the Ge-epilayer especially for C where no liquid phase diffusion or movement could be detected.
Characteristics of In0.7Ga0.3As MOS Capacitors Obtained using Hydrochloric Acid Treatment, Ammonium Sulfide Passivation, Methanol Treatment, and Forming Gas Annealing
(2019-08-14)
Chung, Sheng-Ti
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Huang, Yi-Chin
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Fu, Yen-Chun
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Lee, Yao-Jen
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Chao, Tien-Sheng
This paper proposes a chemical pre-treatment process to reduce sulfate prior to atomic layer deposition of Al2O3 gate dielectrics on n-doped In0.7Ga0.3As layers to form metal oxide semiconductor capacitors (MOSCAPs). Cleaning with methanol was done after hydrogen chloride etching and ammonium sulfide passivation. X-ray photoelectron spectroscopy performed on the sample with methanol cleaning indicated that its native oxide regrowth was effectively prevented on the sulfur-passivated In0.7Ga0.3As surface under air exposure. By analysis using atomic force microscopy of the sample cleaned using methanol, no further increase of surface roughness was observed after 5 months of air exposure. In addition, a mid-gap interface defect density (D-it) of 1.3 x 10(12) cm(-2) eV(-1) was obtained from this sample. After forming gas annealing (FGA), the D-it was improved significantly, to a value below 10(12) cm(-2) eV(-1). The obtained data indicate that the combination of chemical pre-treatment and FGA is advantageous to passivating the trap states on In0.7Ga0.3As MOSCAPs. (C) 2019 The Electrochemical Society.
Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing
(2020-01-01)
Chung, Sheng-Ti
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Lee, Yao-Jen
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Chao, Tien-Sheng
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電子物理學系
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Department of Electrophysics
In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing ferroelectric effects. The ferroelectric layers were deposited on JL-FinFETs. The poly-Si junctionless FinFETs (JL-FinFETs) with HfZrO were successfully fabricated and demonstrated. The subthreshold slope (S.S.) of JL-FinFETs with HfZrO was very sensitive to post-metal annealing (PMA) conditions and fin width. With PMA at 700 & x00B0;C, steeper S.S. and I_on& x002F;I_off> 10(7) could be obtained owing to the ferroelectric effect. JL-FinFETs with PMA at 700 & x00B0;C possessed lower I_off and offered the promise of higher integration flexibility for Si CMOS compatible process for future applications. Besides, the JL-FinFETs with forming gas annealing (FGA) had a small hysteresis and achieved the improved S.S.
Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal
(2014)
Wu, Chien-Ting
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Lee, Yao-Jen
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Hsueh, Fu-Kuo
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Sung, Po-Jung
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Cho, Ta-Chun
A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.
Comparing RTA and Laser SPE & LPE Annealing of Ge-epi with Si, Sn & C Implantation for Well Mobility/Strain Engineering
(2019-01-01)
Borland, John
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Chaung, Shang-Shuin
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Tseng, Tseung-Yuen
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Joshi, Abhijeet
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Basol, Bulent
Comparisons on performance improvement by nitride capping layer among different channel directions nMOSFETs
(2007)
Tsai, Tzu-, I
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Lee, Yao-Jen
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Chen, King-Sheng
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Wang, Jeff
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Hsueh, Fu-Kuo
Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
(2015)
Lee, Yao-Jen
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Hou, Fu-Ju
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
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Kao, Kuo-Hsing
We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.
Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing
(2011-02-01)
Lee, Yao-Jen
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
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Lin, Ho-Ming
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Wu, Shich-Chuang
Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120 degrees C to 140 degrees C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150 degrees C reduction in maximum temperature at the same activation concentration (about 2 x 10(19) cm(-3)) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.
Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
(2020-01-01)
Sung, Po-Jung
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Su, Chun-Jung
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Lo, Shih-Hsuan
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Hsueh, Fu-Kuo
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Lu, Darsen D.
In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I-D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I-d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V-D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.