Browsing by Author "Liang, BS"

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A hardware-efficient architecture for 3-D graphics processor
(1995)
Liang, BS
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Nieh, YC
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Niou, YP
;
Jen, CW
;
Chuang, G
In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.
A project model for software development
(2000-05-01)
Liang, BS
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Chen, JN
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Wang, FJ
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
Uncertainty and dynamic changes in a software project cause iterations during development and the need for decision-making in planning and controlling a project. This paper presents a Software Project Review and Evaluation Model, SPREM, a superset of CPM/PERT which extends CPM/PERT's notation to four types of vertices (AA, AX, XA, and XX vertices) to express the non-deterministic and iterative behaviors of software engineering projects. Several behavioral properties of SPREM and analysis of them are discussed. For example, the enaction capability can be used to evaluate the possibility that a vertex will enact processes beforehand. Project managers can revise a SPREM graph to rescue dead vertices before project execution. Furthermore, enaction ordering allows project managers to calculate the dependency between processes to be enacted. This might help in computing important information such as critical paths among these processes.
An area and time efficient adder for multiple additions with different word-length
(1997)
Liang, BS
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Nieh, YC
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Jen, CW
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交大名義發表
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電子工程學系及電子研究所
To calculate multiple independent additions with different word-length by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision are usually occurring in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization.
Base model transmission for 3D graphics in a network environment
(2002-05-01)
Liang, BS
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A base model should be transmitted First in progressive transmission schemes, and its transmission delay dominates initiation time for rendering. To reduce the initiation time, we restructure the base model to transmit visible vertices and triangles for some specific viewpoints first. and therefore clients can start rendering when parts of model file are received, Simulation results show that only 37.4%. - 51.3%, of model file are required to start rendering. and hence the initiation time is significantly reduced.
Computation-effective 3-D graphics rendering architecture for embedded multimedia system
(2000-01-01)
Liang, BS
;
Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new architecture is proposed to realize 3-D graphics rendering for embedded multimedia system. Because only 20% to 83% triangles in original 3-D object models are risible by simulation, our architecture is designed to eliminate the redundant operations on invisibly triangles without image quality loss. The simulation and analysis results shows that this architecture can save 5% to 60.3% CPU operations compared with traditional architectures.
Computation-effective 3-D graphics rendering architecture for embedded multimedia system
(2000-08-01)
Liang, BS
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new architecture is proposed to realize 3-D graphics rendering for embedded multimedia system. Because only 20% to 83% triangles in original 3-D object models are visible by simulation, our architecture is designed to eliminate the redundant operations on invisible triangles without image quality loss. It bases on our index rendering and enhanced deferred lighting approaches, and its feature is dual pipeline rendering architecture. The simulation and analysis results show that this architecture can save up to 63.4% CPU operations compared with traditional architectures.
Enacting a software development process
(1997)
Chen, MF
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Liang, BS
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Lin, RJR
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Wang, FJ
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交大名義發表
A good process management system helps the project members develop software projects. This paper introduces a Software Process Engineering Environment, SPEE. In SPEE, the process designer designs the process definition and project plan in a Process LANguage, PLAN, under a Process Definition Editor, PDE. A software project is developed on a Process Aided Software process enactment Environment, PASE. PASE provides development guidance, activity enforcement, process automation, tool invocations, and execution feedback for process enactment. SPEE, composed on PDE, PLAN, and PASE, provides helps from the plan to the end of a software project.
Index rendering: Hardware-efficient architecture for 3-D graphics in multimedia system
(2002-09-01)
Liang, BS
;
Lee, YC
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Yeh, WC
;
Jen, CW
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電子工程學系及電子研究所
Real-time three-dimensional (3-D) graphics emerges rapidly in multimedia applications, but it suffers from requirements for huge computation, high bandwidth, and large buffer. In order to achieve hardware efficiency for 3-D graphics rendering, we propose a novel approach named index rendering. The basic concept of index rendering is to realize 3-D rendering pipeline by using asynchronous multi-dataflows. Because triangle information can be divided into several parts with each part capable of being transferred independently and asynchronously. At last, all data are converged by the index to generate the final image. Index rendering approach can eliminate unnecessary operations in traditional 3-D graphics pipeline. The unnecessary operations are caused by the invisible pixels and triangles in the 3-D scene. Previous work, deferred shading, eliminates the operations relating to invisible pixels, but it requires huge tradeoffs in bandwidth and buffer size. With index rendering, we can eliminate operations on both invisible pixels and triangles with less tradeoffs as compared with deferred shading approach. The simulation and analysis results show that the index rendering approach can reduce 10%-70% of lighting operations when using flat and Gouraud shading process and decrease 30%-95% when using Phong shading. Furthermore, it saves 70% of buffer size and 50%-70% of bandwidth compared with deferred shading approach. The result also indicates that this approach of index rendering is especially suitable for low-cost portable rendering device. Hence, index rendering is a hardware-efficient architecture for 3-D graphics, and it makes rendering hardware easier to be integrated into multimedia system, especially in system-on-a-chip (SOC) design.
Speed up of rendering pipeline by deferred lighting and triple queue structure
(2001-10-25)
Liang, BS
;
Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Redundant operations and stalls prevent a rendering pipeline from full-speed operation. To speed up the rendering pipeline, a triple queue structure is proposed to smooth the pipeline and to obtain benefit from deferred lighting. The results of cycle-accurate simulation show that the proposed structure can reduce rendering cycles to 52.9% in small size queues.