Browsing by Author "Lin, Jer-Yi"

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Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs
(2017-07-01)
Hsieh, Dong-Ru
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Lin, Jer-Yi
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Kuo, Po-Yi
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Chao, Tien-Sheng
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電子物理學系
In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n(+) doped poly-Si (DP-Si) fin-channels have been experimentally investigated and comprehensively discussed. The subthreshold behavior and threshold voltage of the PG JL FETs are sensitive to the channel dimensions, especially the channel width. The crystallinity, carrier mobility, and effective carrier concentration in the DP-Si films are dependent on the initial DP-Si film thicknesses, which directly influence the on current and threshold voltage of the PG JL FETs. Based on an evaluation on the subthreshold behavior and the driving current, we found that the PG JL FETs with the low/high aspect ratio (A.R. = channel thickness/channel width) are separately suitable for the low-power/high-performance applications. Among these PG JL FETs, the device with a proper A.R. (3.35) exhibits a relatively steep subthreshold swing (S.S.) of 66 mV/decade and the highest (ON)/(OFF) currents ratio (I-ON/I-OFF) of 1.2 x 10(8) (VD = 1 V). These devices are very promising candidates for future multifunctional 3-D integrated circuit applications.
Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications
(2016)
Hsieh, Don-Ru
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Lin, Jer-Yi
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Kuo, Po-Yi
;
Chao, Tien-Sheng
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電子物理學系
In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) similar to 68 mV/dec., steep average subthreshold swing (A.S.S.) similar to 73 mV/dec., smaller drain induced barrier lowing (DIBL) similar to 9 mV/V, and higher I-on/I-off ratio similar to 1.1 x 10(8) (V-D = 1 V).
High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET
(2016-11)
Hsieh, Dong-Ru
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Lin, Jer-Yi
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Kuo, Po-Yi
;
Chao, Tien-Sheng
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電子物理學系
In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width similar to 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG polySi JL FETs show excellent electrical performance in terms of low gate overdrive voltage (V-G-V-TH = 2 V), extremely nearideal subthreshold swing (S.S.) similar to 68 mV/decade, steep average subthreshold swing (A.S.S.) similar to 73 mV/decade, smaller drain-induced barrier lowering similar to 9 mV/V, a higher ON/OFF current ratio similar to 1.1 x 10(8) (VD = 1 V), and a better field-effect mobility (mu(FE)) similar to 35 (cm(2)/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications.
High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique
(2017-02)
Hsieh, Dong-Ru
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Kuo, Po-Yi
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Lin, Jer-Yi
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Chen, Yi-Hsuan
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Chang, Tien-Shun
In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) similar to 110mV/dec., an extremely small drain induced barrier lowing (DIBL) similar to 12.2mVV(-1), and a high on/off ratio similar to 10(7) (V-D = 1V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.
Impact of Crystallization Method on Poly-Si Tunnel FETs
(2015-10-01)
Chen, Yi-Hsuan
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Ma, William Cheng-Yu
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Lin, Jer-Yi
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Lin, Chun-Yen
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Hsu, Po-Yang
In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (N-it) and bulk traps (N-GB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit similar to 4.5x higher ON-state current I-ON, subthreshold swing reduction Delta S.S. similar to 202 mV/decade, and larger similar to 7.2x ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced N-it similar to 0.60x and a reduced N-GB similar to 0.36x, respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics.
Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing
(2015)
Kuo, Po-Yi
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Lin, Jer-Yi
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Chao, Tien-Sheng
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電子物理學系
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Department of Electrophysics
The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (D-NW) - length (L-NW) x width (W-NW) x thickness (T-NW) - to 80nmx13nmx3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) similar to 61mV/dec., steep driving swing (D.S.) similar to 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.
Investigation of Hot Carrier Reliability of Ultrathin Poly-Si Nanobelt Junctionless (UTNB-JL) Transistors on Different Underlying Insulators
(2016)
Chang, Jen-Hong
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Chung, Chun-Chih
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Lin, Jer-Yi
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Chao, Tien-Sheng
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電子物理學系
In this work, we investigate the hot carrier stress (HCS) of ultrathin poly-Si nanobelt junctionless transistors on different insulator (TEOS and Si3N4). Time exponent n suggests the oxide trap charge is the dominant mechanism. The subthreshold slope (S.S.) is improved by acceptor-like interface states generated after HCS, and different S.S. improvement between JL_O and JL_N is caused by surface roughness of channel films resulting from nucleation during channel deposition in LPCVD step.
Junctionless FETs With a Fin Body for Multi-V-TH and Dynamic Threshold Operation
(2018-08-01)
Kumar, Malkundi Puttaveerappa Vijay
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Lin, Jer-Yi
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Kao, Kuo-Hsing
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Chao, Tien-Sheng
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電子物理學系
In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+FB can control the electrostatic potential of the channel more efficiently for multi-V-TH (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor (gamma) is predicted for wide range V-TH modulation. Thanks to the stronger potential coupling between the channel and FB, the proposeddevice exhibits gamma improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi-V-TH operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption.
Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability
(2018-01-01)
Lin, Jer-Yi
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Kumar, Malkundi Puttaveerappa Vijay
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Chao, Tien-Sheng
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電子物理學系
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Department of Electrophysics
In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drivestress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits.
Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
(2016-12)
Lin, Jer-Yi
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Kuo, Po-Yi
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Lin, Ko-Li
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Chin, Chun-Chieh
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Chao, Tien-Sheng
In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 degrees C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing similar to 75 mV/decade, low drain-induced barrier lowering similar to 33 mV/V, and high on/off currents ratio (I-ON/I-OFF) similar to 7 x 10(6) can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.
Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations
(2018-09-01)
Lin, Jer-Yi
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Tsai, Chan-Yi
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Shen, Chiuan-Huei
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Chung, Chun-Chih
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Kumar, Malkundi Puttaveerappa Vijay
In this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n(+) active device layer, are successfully demonstrated to show a better performance compared with conventional tri-gate nanosheet (NS) JLTs. Because the potential barrier between the n-channel and p-body in the VC-JLT can be controlled by the gate, the effective conduction channel behaves as a "variable" channel, in which the conduction thickness is thinner or thicker than the physical n(+) thickness for the OFF or ON state, respectively. Consequently, the VC-JLT can turn OFF more efficiently due to the enhanced volume depletion and turn ON with a smaller series resistance owing to the augmented conduction volume. In addition, for the first time, the impact of the body doping concentration is investigated and the performance sensitivities of VC-JLTs in terms of I-ON, V-T, S.S., and DIBL are discussed with respect to the dopant redistribution. Furthermore, the quality factor (I-ON/S.S.) of the VC-JLT is also benchmarked with recently published poly-Si JLTs, showing that the proposed VC-JLT exhibits good S.S. and a record I-ON , which makes it as a promising device for 3-D integrated nanoelectronics.
Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit
(2018-02-01)
Chung, Chris Chun-Chih
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Shen, Chiuan-Huei
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Lin, Jer-Yi
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Chin, Chun-Chieh
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Chao, Tien-Sheng
We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high-k metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.