Browsing by Author "Lu, CY"

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A low noise composite-channel metamorphic HEMT for wireless communication applications
(2003)
Lu, CY
;
Chen, KS
;
Lee, HM
;
Chang, EY
;
Chen, SH
A composite-channel Metamorphic high electron mobility transistor (MHEMT) was developed for low noise high linearity application. The MHEMT was grown by Molecular Beam Epitaxy (MBE) on GaAs substrates with InAlAs graded buffer. The composite-channel layers in the MHEMT include a top In0.55Ga0.45As layer, a middle In0.67Ga0.33As layer, and a bottom In0.55Ga0.45As layer. The design of this structure provides better electron confinement in the channel with less impact ionization as compared to conventional dual delta doped MHEMTs. This results in devices with higher linearity and drain to gate voltage as compared to the conventional metamorphic HEMTs. The 0.25x160 mum(2) device with the novel channel structure exhibits a maximum frequency of oscillation f(max) of 290 GHz and a current gain cut-off frequency f(t) of 110 GHz. The noise figure of the device at 6 GHz is 0.23 dB and the associated gain was 15.06 dB. The IP3 of the device at 6 GHz is 19.67 dBm. The composite channel metamorphic HEMT shows great potential for high linearity and low noise application at high frequencies.
A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell
(2004-09-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n(+) unction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V-t) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.
A novel fully CMOS process compatible PREM for SOC applications
(2005-03-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.
A novel operation method to avoid overerasure in a scaled trapping-nitride localized charge storage flash memory cell and its application for multilevel programming
(2006-04-01)
Tsai, WJ
;
Zous, NK
;
Wang, TH
;
Ku, YHJ
;
Lu, CY
By using the charge pumping technique, it was found that the injected-hole occupied percentage increases with respect to the whole channel, and overerasure thus happens in a scaled trapping-nitride storage Flash memory cell. Such overerasure can be avoided or can be recovered if the cell is suitably biased during the erase operation. Moreover, the erase threshold voltage can be well controlled by the applied erase gate voltage. The reason is that both the channel-hot electrons and the band-to-band tunneling-induced hot holes would inject at the same time and are in balance as a specific surface potential is achieved. Based on this study, a self-limited soft program, as well as a self-saturated erase scheme, is proposed. Applications of this concept to multilevel programming are also demonstrated.
A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications
(2005-04-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Chen, MS
A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is-developed. The memory bit size of 0.046 mu m(2) is fabricated based on 0.13-mu m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V-t in erase while programming is done by lowering a local V-t through hand-to-hand tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.
A novel soft-program for a narrow erased state Vt distribution, read disturbance suppression and over-program annihilation in multilevel cell flash memories
(2003-04-01)
Yeh, CC
;
Fan, TH
;
Lu, TC
;
Wang, TH
;
Pan, S
In floating gate flash memories, anode hot hole injection induced by the channel FN erase will result in tunnel oxide, degradation, severe read disturbance and an abnormally fast program. All of these issues are critical for multilevel cell (MLC) flash memory design, which requires precise threshold voltage placement, good data retentivity and programming controllability. In this paper, a novel soft-program scheme is proposed to narrow the threshold voltage distribution in the first level. Cycling-induced read disturbance and programming inaccuracy are also reduced. This technique is essential for the application of more-than-2-bit MLC, flash memories.
A study of the recirculating flow in planar, symmetrical branching channels
(2006-01-20)
Tsui, YY
;
Lu, CY
;
機械工程學系
;
Department of Mechanical Engineering
A numerical method is employed to examine the now in symmetrical, two-dimensional branches of Y shape and Tee shape. The methodology is based oil a pressure-correction procedure within the frame of unstructured grids. Specified pressures are imposed at the outlets of the two branches. The area ratio of the branch is allowed to vary in the range of 2-3. Separation of the flow in the bifurcating region is inevitable. Willi equal Millet pressures, symmetrical flow patterns prevail except for the Y type branch Under the conditions of high Reynolds numbers and large area ratios. This implies that the Y-branch flow is more sensitive to small disturbances. It is shown that with a slightly higher pressure imposed oil one of the two branches the structure Of the recirculating flow for the Y type is greatly affected and the flow rate is reduced dramatically in the high-pressure branch channel. In contrast, the influence on the Tee type branch is much lower since the flow behaves like a jet impinging oil a confined duct. Copyright (c) 2005 John Wiley & Sons, Ltd.
Ambipolar Schottky barrier silicon-on-insulator metal-oxide-semiconductor transistors
(2003-02-01)
Lin, HC
;
Wang, MF
;
Lu, CY
;
Huang, TY
;
電子工程學系及電子研究所
A novel Schottky barrier silicon-on-insulator metal-oxide-semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 10(8) and 10(7) are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization. (C) 2002 Elsevier Science Ltd. All rights reserved.
An endurance evaluation method for flash EEPROM
(2004-05-01)
Zous, NK
;
Chen, YJ
;
Chin, CY
;
Tsai, WJ
;
Lu, TC
Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V-T rollup, and cycling V-T window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V-T rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted Delta V-T degradation slope during constant FN stress can be applied quantitatively to predict the V-T window closure during Flash cell cycling.
Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique
(2006-01-01)
Gu, SH
;
Wang, TH
;
Lu, WP
;
Ting, WC
;
Ku, YHJ
In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.
Device characteristics and aggravated negative bias temperature instability in p-channel metal-oxide-semiconductor field-effect transistors with uniaxial compressive strain
(2006-04-01)
Lu, CY
;
Lin, HC
;
Chang, YF
;
Huang, TY
;
電子工程學系及電子研究所
P-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) featuring poly-SiGe gates and compressive strain channels were investigated. The compressive strain in the channel was deliberately induced in this study by a plasmaenhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer over the gate. Our results indicate for the first time that, while strain channel engineefing serves as an effective method to enhance drive current for scaled complementary metal-oxide-scmiconductor (CMOS) devices consistent with literature reports, it also simultaneously aggravates the negative bias temperature instability (NBTI) of scaled devices. The aggravated NBTI behavior is ascfibed to a higher amount of hydrogen incorporation during SiN deposition as well as a higher strain energy stored in the channel. Saturation phenomena in the shift of threshold voltage and generation of interface states are observed at high stress temperatures and long stress times. Moreover, transconductance degradation in devices with SiN capping is greatly aggravated under high temperature stress.
Fabrication and characteristics of high-speed oxide-confined VCSELs using InGaAsP-InGaP strain-compensated MQWs
(2004-12-01)
Chang, YH
;
Kuo, HC
;
Lai, FI
;
Chang, YA
;
Lu, CY
This paper presents the fabrication and characteristics of high-performance 850-mn InGaAsP-InGaP strain-compensated multiple-quantum-well (MQW) vertical-cavity surface-emitting lasers (VCSELs). The InGaAsP-InGaP MQW's composition was optimized through theoretical calculations, and the growth condition was optimized using photoluminescence. These VCSELs exhibit superior performance with characteristics threshold currents similar to0.4 mA and slope efficiencies similar to0.6 mW/mA. The threshold current change with temperature is less than 0.2 mA, and the slope efficiency drops less than similar to30% when the substrate temperature is raised from room temperature to 85degreesC. A high modulation bandwidth of 14.5 GHz and a modulation current efficiency factor of 11.6 GHz/(mA) (1/2) are demonstrated. The authors have accumulated life test data up to 1000 h at 70degreesC/8 mA.
High-performance P-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions
(2003-02-01)
Lin, HC
;
Wang, MF
;
Hou, FJ
;
Lin, HN
;
Lu, CY
A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in, the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by, the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.
High-speed (> 10 Gbps) 850 nm oxide-confined vertical cavity surface emitting lasers (VCSELs) with a planar process and reduced parasitic capacitance
(2004-07-01)
Chang, YH
;
Lai, FI
;
Lu, CY
;
Kuo, HC
;
Yu, HC
This study reports the high-speed performance of 850 nm oxide-confined vertical cavity surface emitting lasers (VCSELs) with a planar process and reduced parasitic capacitance. The parasitic capacitance of VCSELs was reduced using additional proton implantation. The small signal modulation bandwidth which was restricted by electric parasitic capacitance expanded from 2.3 GHz to 9 GHz after proton implantation. The reflection coefficient showed that the electric parasitic pole exceeded 20 GHz. An eye diagram of VCSEL with reduced parasitic capacitance operating at 10 Gps with 6 mA bias and 6 dB extinction ratio showed a very clean eye with a jitter of less than 20 ps.
Highly reliable liquid-phase deposited SiO2 with nitrous oxide plasma post-treatment for low temperature processed poly-Si TFT's
(1998)
Yeh, CF
;
Chen, DC
;
Lu, CY
;
Liu, C
;
Lee, ST
Low temperature (similar to 300 degrees C) N2O plasma annealing for liquid-phase deposited (LPD) gate oxide has been proposed for the first time. Physicochemical and electrical characterizations show that the N2O-treated LPD-SiO2 improves breakdown field, interface state density, and Si-rich phenomenon. This novel technology has been also successfully applied to LTP poly-Si TFT's, which reveal excellent characteristics and reliability. It is believed that the N2O plasma post-treatment not only improves the oxide quality, but also passivates the trap states in poly-Si channel.
Highly reliable liquid-phase-deposited SiO2 with nitrous oxide plasma post-treatment for low-temperature-processed polysilicon thin film transistors
(2002-10-01)
Yeh, CF
;
Chen, DCH
;
Lu, CY
;
Liu, C
;
Lee, ST
Low-temperature ( similar to 300 C) N2O-plasma post-treatment for liquid-phase-deposited (LPD) gate oxide has been proposed for the first time. This treatment successfully takes the place of conventional furnace annealing in O-2 ambient. Results of physicochemical and electrical characteristics shock that N2O-plasma post-treated LPD-SiO2 has a high electrical breakdown field and low interface State density. In addition. N2O-plasma treatment also improves the Si-rich phenomenon of LPD-SiO2. From the comparison with pure N2O-plasma oxidation film, LPD-SiO2 with its short re-oxidation time in N2O plasma plays an important role in relieving interfacial stress. Finally, the novel technology is applied to the gate oxide of low-temperature-processed (LTP) polysilicon thin film transistors (poly-Si TFTs). The device performance reveals excellent electrical characteristics, and the reliability shows a satisfactory result. as well as the gate oxide reliability. It is believed that the N2O-plasma post-treatment not only improves the oxide quality, but also effectively passivates the trap states of poly-Si TFTs.
Impacts of uniaxial compressive strain on dynamic negative bias temperature instability of p-channel MOSFETs
(2006)
Lu, CY
;
Lin, HC
;
Huang, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ynamic negative bias temperature instability (DNBTI) characteristics of p-metal oxide semiconductor field-effect transistors (p-MOSFETs) with compressive channel strain induced by a SiN-capping layer were investigated. Although the SiN-capping is effective in boosting the device drive current, it may concomitantly worsen DNBTI characteristics. This is ascribed to higher hydrogen content incorporated during SiN deposition as well as higher strain energy stored in the channel. A strong dependence on the ac stress frequency is also observed for the SiN-capped devices, which is ascribed to excess hydrogen species contained in the strained devices. Finally, our experimental results also suggest that the aggravated NBTI in the strained devices could be alleviated by high frequency operation. (c) 2006 The Electrochemical Society.
Improving high-temperature performance in continuous-wave mode InGaAsN/GaAsN ridge waveguide lasers
(2005-06-01)
Chang, YA
;
Kuo, HC
;
Lu, CY
;
Kuo, YK
;
Wang, SC
Continuous-wave (CW) mode operation InGaAsN/GaAsN double-quantum-well lasers with a laser wavelength of 1.295 mu m are demonstrated by metal-organic chemical vapour deposition (MOCVD). With the use of a high-bandgap GaAs0.9P0.1 into the active region before the growth of p-type layers, a room temperature (RT) threshold current of 99 mA and the characteristic temperature (TO) values of 155 K in a temperature range of 25-95 degrees C and 179 K in a temperature range of 25-85 degrees C are obtained from a 4 x 1000 mu m(2) ridge waveguide uncoated laser diode. The To value of the conventional structure without the high-bandgap GaAs0.9P0.1 is 118 K in a temperature range of 25-95 degrees C. High-temperature performance is improved and the results of numerical analysis suggest that it may be attributed to the reduced electronic leakage current.
Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique
(2004)
Gu, SH
;
Wang, MT
;
Chan, CT
;
Zous, NK
;
Yeh, CC
The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find prograrnmed charge spreads further into the channel with program/erase cycle number.
Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology
(2004-09-01)
Zous, NK
;
Lee, MY
;
Tsai, WJ
;
Kuo, A
;
Huang, LT
The negative threshold voltage (V-t) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V-t shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V-t shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V-t drift is proposed.