Browsing by Author "Wan, Chia-Chen"

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3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
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Lu, Yu-Lun
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Hsueh, Fu-Kuo
;
Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
3D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating Current
(2013-01-01)
Hsu, Chung-Wei
;
Wan, Chia-Chen
;
Wang, I-Ting
;
Chen, Mei-Chin
;
Lo, Chun-Li
The 3D double-layer vertical RRAM with ultralow sub-mu A operating current and high self-rectifying ratio over 10(3) has been demonstrated for the first time. This Ta/TaOx/TiO2/Ti interfacial switching device overcomes the intrinsic trade-off between operating current and variability in filamentary RRAMs and shows promising potential for high-density data storage.
Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
(2014-04-25)
Hsu, Chung-Wei
;
Wang, Yu-Fen
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Wan, Chia-Chen
;
Wang, I-Ting
;
Chou, Chun-Tse
Three-dimensional vertical resistive-switching random access memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive storage-class memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 10(3) with a sub-mu A operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 10(15) cycles at 100 degrees C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage memory by exploiting a unique tradeoff between retention time and endurance.
Impacts of a buffer layer and hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layer
(2007)
Tsai, Tzu-, I
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Lee, Yao-Jen
;
Chen, King-Sheng
;
Wang, Jeff
;
Wan, Chia-Chen
Reliability of strained-channel NMOSFETs with SiN capping layer on Hi-wafers with a thin LPCVD-TEOS buffer layer
(2007)
Tsai, Tzu-, I
;
Lee, Yao-Jen
;
Chen, King-Sheng
;
Wang, Jeff
;
Wan, Chia-Chen
Suspended Ge Gate-All-Around Nanowire nFETs with Junction Isolation on Bulk Si
(2016)
Wan, Chia-Chen
;
Luo, Guang-Li
;
Hsu, Shu-Han
;
Hung, Kuo-Dong
;
Chu, Chun-Lin
Replacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility {111} surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I-ON/I-OFF of 5x10(5), which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process.