Browsing by Author "Wang, TH"

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A comparative study of SILC transient characteristics and mechanisms in FN stressed and hot hole stressed tunnel oxides
(1999)
Zous, NK
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Wang, TH
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Yeh, CC
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Tsai, CW
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Huang, CM
The mechanisms and transient characteristics of hot hole stress and FN stress induced excess leakage currents in tunnel oxides are investigated. Hot hole SILC is found to have a more pronounced transient effect. The transient is attributed to positive oxide charge detrapping and thus annihilation of positive charge-assisted tunneling current. The positive charge assisted tunneling current can be annealed by substrate hot electron injection. The DC and transient components in FN SILC are also discussed.
A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's
(1999-09-01)
Wang, TH
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Chiang, LP
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Zous, NK
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Hsu, CF
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Huang, LY
The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V-gs such as drain-to-source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account, The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current,:and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Angstrom) n-MOSFET's, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Angstrom) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.
A global pinching theorem for surfaces with constant mean curvature in S-3
(2001-01-01)
Hsu, YJ
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Wang, TH
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應用數學系
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Department of Applied Mathematics
Let M be a compact immersed surface in the unit sphere S-3 with constant mean curvature H. Denote by phi the linear map from T-p(M) into Tp(M), phi = A - H/2 I, where A is the linear map associated to the second fundamental form and I is the identity map. Let Phi denote the square of the length of phi. We prove that if parallel to Phi parallel to (L2) less than or equal to C, then M is either totally umbilical or an H(r)-torus, where C is a constant depending only on the mean curvature H.
A global pinching theorem for surfaces with constant mean curvature in S-3
(2002)
Hsu, YJ
;
Wang, TH
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應用數學系
;
Department of Applied Mathematics
Let M be a compact immersed surface in the unit sphere S-3 with constant mean curvature H. Denote by phi the linear map from T-p(M) into Tp(M), phi = A - H/2 I, where A is the linear map associated to the second fundamental form and I is the identity map. Let Phi denote the square of the length of phi. We prove that if parallel to Phi parallel to (L2) less than or equal to C, then M is either totally umbilical or an H(r)-torus, where C is a constant depending only on the mean curvature H.
A new technique to extract oxide trap time constants in MOSFET's
(1996-08-01)
Wang, TH
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Chang, TE
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Chiang, LP
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Huang, C
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電子工程學系及電子研究所
A new technique to determine oxide trap time Constants in a 0.6 mu m n-MOSFET subject to hot electron stress has been proposed, In this method, we used GIDL current as a direct monitor of the oxide charge detrapping-induced transient characteristics. An analytical model relating the GIDL current evolution to oxide trap time constants was derived, Our result shows that under a field-emission dominant oxide charge detrapping condition, V-gs = -4 V and V-ds = 3 V, the hot electron stress generated oxide traps exhibit two distinct time constants from seconds to several tens of seconds.
A new technique to measure an oxide trap density in a hot carrier stressed n-MOSFET
(1997)
Wang, TH
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Chiang, LP
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Chang, TE
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Zous, NK
;
Shen, KY
We have proposed a new measurement technique to characterize the hot carrier stress generated oxide traps in a n-MOSFET by measuring subthreshold current. In this technique, a specially designed measurement consisting of a series of oxide charge detrapping and subthreshold current measurement phases was performed. An analytical model accounting for the temporal evolution of subthreshold current due to oxide charge detrapping was derived. Our study shows that this method is extremely sensitive to an oxide charge variation. By using this method, the oxide trap growth rates by hot electron stress and hot hole stress were measured.
A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell
(2004-09-01)
Yeh, CC
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Wang, TH
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Tsai, WJ
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Lu, TC
;
Liao, YY
The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n(+) unction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V-t) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.
A novel fully CMOS process compatible PREM for SOC applications
(2005-03-01)
Yeh, CC
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Wang, TH
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Tsai, WJ
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Lu, TC
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Liao, YY
A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.
A novel operation method to avoid overerasure in a scaled trapping-nitride localized charge storage flash memory cell and its application for multilevel programming
(2006-04-01)
Tsai, WJ
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Zous, NK
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Wang, TH
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Ku, YHJ
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Lu, CY
By using the charge pumping technique, it was found that the injected-hole occupied percentage increases with respect to the whole channel, and overerasure thus happens in a scaled trapping-nitride storage Flash memory cell. Such overerasure can be avoided or can be recovered if the cell is suitably biased during the erase operation. Moreover, the erase threshold voltage can be well controlled by the applied erase gate voltage. The reason is that both the channel-hot electrons and the band-to-band tunneling-induced hot holes would inject at the same time and are in balance as a specific surface potential is achieved. Based on this study, a self-limited soft program, as well as a self-saturated erase scheme, is proposed. Applications of this concept to multilevel programming are also demonstrated.
A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications
(2005-04-01)
Yeh, CC
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Wang, TH
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Tsai, WJ
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Lu, TC
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Chen, MS
A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is-developed. The memory bit size of 0.046 mu m(2) is fabricated based on 0.13-mu m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V-t in erase while programming is done by lowering a local V-t through hand-to-hand tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.
A novel soft-program for a narrow erased state Vt distribution, read disturbance suppression and over-program annihilation in multilevel cell flash memories
(2003-04-01)
Yeh, CC
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Fan, TH
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Lu, TC
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Wang, TH
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Pan, S
In floating gate flash memories, anode hot hole injection induced by the channel FN erase will result in tunnel oxide, degradation, severe read disturbance and an abnormally fast program. All of these issues are critical for multilevel cell (MLC) flash memory design, which requires precise threshold voltage placement, good data retentivity and programming controllability. In this paper, a novel soft-program scheme is proposed to narrow the threshold voltage distribution in the first level. Cycling-induced read disturbance and programming inaccuracy are also reduced. This technique is essential for the application of more-than-2-bit MLC, flash memories.
A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs - From single electron emission to PBTI recovery transient
(2006-05-01)
Wang, TH
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Chan, CT
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Tang, CJ
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Tsai, CW
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Wang, HCH
A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.
An endurance evaluation method for flash EEPROM
(2004-05-01)
Zous, NK
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Chen, YJ
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Chin, CY
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Tsai, WJ
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Lu, TC
Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V-T rollup, and cycling V-T window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V-T rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted Delta V-T degradation slope during constant FN stress can be applied quantitatively to predict the V-T window closure during Flash cell cycling.
Analysis of high-field hole transport characteristics in Si1-xGex alloys with a bond orbital band structure
(1996-01-01)
Liou, TS
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Wang, TH
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Chang, CY
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交大名義發表
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電子工程學系及電子研究所
We present an analysis of high-field hole transport in strained Si1-xGex alloys using a Monte Carlo technique. A bond orbital model is employed to calculate the valence-band structure in the simulation so that the transport behavior of high-energy holes can be described accurately. The model combines the k . p and the tight binding methods and contains no fitting parameters. The spin-orbit interaction and lattice-mismatch-induced biaxial compressive strain are included in the model. The steady state hole drift velocity and the impact ionization rate are calculated as a function of an electric field up to 500 kV/cm. Good agreement between experiment and simulation is obtained. (C) 1996 American Institute of Physics.
Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices
(2002-01-01)
Wang, HCH
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Wang, CC
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Diaz, CH
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Liew, BK
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Sun, JYC
Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced as compared to the one without TED. The reason is that the TED effect can yield a more graded n(-) LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field
Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias
(2003-04-01)
Tsai, CW
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Chen, MC
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Ku, SH
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Wang, TH
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電子工程學系及電子研究所
Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel thus substantially increasing channel hot electron energy. Measured hot electron gate-current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten time's more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.
Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique
(2006-01-01)
Gu, SH
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Wang, TH
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Lu, WP
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Ting, WC
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Ku, YHJ
In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.
Characterization of various stress-induced oxide traps in MOSFET's by using a novel transient current technique
(1997)
Wang, TH
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Chiang, LP
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Zous, NK
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Chang, TE
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Huang, C
A new oxide trap characterization technique by employing a two-phase subthreshold current measurement has been developed. By varing the gate bias and the drain bias in measurement, the field and temperature dependences of oxide charge detrapping and the spatial distributions of various stress induced oxide traps are characterized.
Characterization of various stress-induced oxide traps in MOSFET's by using a subthreshold transient current technique
(1998-08-01)
Wang, TH
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Chiang, LP
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Zous, NK
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Chang, TE
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Huang, C
An oxide trap characterization technique by measuring a subthreshold current transient is developed, This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps, Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized, By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained, Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant.
Comparison of oxide breakdown progression in ultra-thin oxide silicon-on-insulator and bulk metal-oxide-semiconductor field effect transistors
(2004-09-15)
Chen, MC
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Ku, SH
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Chan, CT
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Wang, TH
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電子工程學系及電子研究所
Enhanced oxide breakdown progression in ultra-thin oxide silicon-on-insulator p-type metal-oxide-semiconductor field-effect transistors is observed, as compared to bulk devices. The enhanced progression is attributed to the increase of hole stress current resulting from breakdown induced channel carrier heating in a floating-body configuration. Numerical analysis of hole tunneling current and hot carrier luminescence measurement are performed to support our proposed theory. This phenomenon is particularly significant to the reliability of devices with ultra-thin oxides and low operation gate voltage. (C) 2004 American Institute of Physics.