Browsing by Author "Wu, Yung-Chun"

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A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals
(2013-02-01)
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Hung, Min-Feng
;
Tang, Zih-Yun
;
Cheng, Ya-Chi
This work presents gate-all-around (GAA) polycrystalline silicon (poly-Si) nanowires (NWs) channel poly-Si/SiO2/Si3N4/SiO2/poly-Si (SONOS) nonvolatile memory (NVM) with a self-assembled Si nanocrystal (Si-NC) embedded charge trapping (CT) layer. Fabrication of the Si-NCs is simple and compatible with the current flash process. The 2-bit operations based on channel hot electrons injection for programming and channel hot holes injection for erasing are clearly achieved by the localized discrete trap. In the programming and erasing characteristics studies, the GAA structure can effectively reduce operation voltage and shorten pulse time. One-bit programming or erasing does not affect the other bit. In the high-temperature retention characteristics studies, the cell embedded with Si-NCs shows excellent electrons confinement vertically and laterally. With respect to endurance characteristics, the memory window does not undergo closure after 10(4) program/erase (P/E) cycle stress. The 2-bit operation for GAA Si-NCs NVM provides scalability, reliability and flexibility in three-dimensional (3D) high-density flash memory applications. (C) 2013 The Japan Society of Applied Physics
A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs
(2016)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Cheng, Chun-Hu
;
Shih, Yi-Jia
This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I-on/I-off current ratio (> 10(9)), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.
A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
Application of fluorine doped oxide (SiOF) spacers for improving reliability in low temperature polycrystalline thin film transistors
(2008-12-01)
Feng, Li-Wei
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Tu, Chun-Hao
;
Wu, Yung-Chun
The novel process of self-aligned fluorine doped oxide (SiOF) spacers on low temperature poly-Si (LTPS) lightly doped drain (LDD) thin film transistors (TFTs) is proposed. A fluorine doped oxide spacers were provided to generate the lower dissociation Si-F bonds adjusted to the interface of the drain which is the largest lateral electric field region for lightly doped drain structure. The stronger Si-F bonds can reduce the bonds broken by impact ionization. It is found that the output characteristics of SiOF spacers TFTs show the superior immunity to kink effect. The degradations in Vth shifting, subthreshold slope, drain current and transconductance of SiOF spacers after DC stress are improved. (C) 2008 Elsevier B.V. All rights reserved.
Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off
(2015-11-02)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Wu, Yi-Kang
;
Shih, Yi-Jia
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.
Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis
(2013-02-01)
Han, Ming-Hung
;
Chang, Chun-Yen
;
Jhan, Yi-Ruei
;
Wu, Jia-Jiun
;
Chen, Hung-Bin
The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (V-th), on current (I-on), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.
Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate
(2015-02-01)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Su, Jun-Ji
;
Shao, Chi-Shen
;
Thirunavukkarasu, Vasanthan
This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.
Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel
(2013-07-01)
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Lu, Nan-Heng
;
Wu, Jia-Jiun
;
Han, Ming-Hung
This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10(8) because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.
Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure
(2007-12-15)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V-th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V-th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V-th shift is improved from -0.3 V to -1.3 V at -14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 degrees C and a 0.8 V memory window after 5 x 10(3) P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. (C) 2007 Elsevier B.V. All rights reserved.
Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
(2014-12-11)
Cheng, Ya-Chi
;
Chen, Hung-Bin
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Su, Jun-Ji
;
Shao, Chi-Shen
;
Wang, Cheng-Ping
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (> 1 mu A/mu m). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I-on/I-off current ratio is over 10(8) A/A for L-g = 1 mu m. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V-th in multi-V-th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO(2) Charge Trapping Layer
(2011-03-01)
Chen, Lun-Jyun
;
Wu, Yung-Chun
;
Chiang, Ji-Hong
;
Hung, Min-Feng
;
Chang, Chin-Wei
This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO(2) charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 mu s. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pigate NWs poly-Si TFT NVM with a Si(3)N(4) charge-trapping layer was also fabricated. Since HfO(2) has a deeper conduction band than Si(3)N(4), the device with the HfO(2) charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si(3)N(4) charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO(2) charge-trapping layer to undergo more P/E cycles than that with the Si(3)N(4) charge-trapping layer.
Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO2 Charge Trapping Layer
(2011-03-01)
Chen, Lun-Jyun
;
Wu, Yung-Chun
;
Chiang, Ji-Hong
;
Hung, Min-Feng
;
Chang, Chin-Wei
This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO2 charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 mu s. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pigate NWs poly-Si TFT NVM with a Si3N4 charge-trapping layer was also fabricated. Since HfO2 has a deeper conduction band than Si3N4, the device with the HfO2 charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si3N4 charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO2 charge-trapping layer to undergo more P/E cycles than that with the Si3N4 charge-trapping layer.
Degradation behaviors of trigate nanowires poly-si TFTs with NH3 plasma passivation under hot-carrier stress
(2007)
Wu, Yung-Chun
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Feng, Li-Wei
;
電子工程學系及電子研究所
This work studies degradation behavior after hot-carrier stress of trigate polysilicon thin-film transistors (poly-Si TFTs) with nanowires. The NH3 plasma passivation effect is also studied on the electrical characteristics after hot-carrier stress. The reliability of poly-Si TFTs with NH3 plasma passivation outperforms that without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pileup of nitrogen at the SiO2/poly-Si interface. The reliability of poly-Si TFTs further improves by using nanowires structure. These findings originate from the fact that the nanowires poly-Si TFT has robust trigate control to reduce the hot-carrier effect due to declining lateral electrical field and its penetration from the drain, and its split nanowire structure has superior NH3 plasma passivation effect. In degradation results under dc and ac stress, it reveals that the NH3 plasma is mostly passivated on deep traps of grain boundaries rather than tail traps.
Device and Circuit Performance Estimation of Junctionless Bulk FinFETs
(2013-06-01)
Han, Ming-Hung
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Chang, Chun-Yen
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Chen, Hung-Bin
;
Cheng, Ya-Chi
;
Wu, Yung-Chun
The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.
Electrical enhancement of solid phase crystallized poly-Si thin-film transistors with fluorine ion implantation
(2006)
Tu, Chun-Hao
;
Chang, Ting- Chang
;
Liu, Po-Tsun
;
Chen, Chih-Hung
;
Yang, Che-Yu
Solid phase recrystallized polycrystalline silicon thin-film transistors (SPC poly-Si TFTs) with fluorine ion implantation were investigated in this study. Electrical characteristics and reliability of the proposed poly-Si TFTs were improved effectively, especially for field effect mobility and off current. The fluorine-ion-implanted poly-Si TFT can suppress the hot carrier multiplication near the drain side, leading to superior endurance to electrical stress compared with conventional poly-Si TFTs. It was found that fluorine ions will pile up at the poly-Si interface during thermal annealing, without the initial deposition of pad oxide. The proposed technology is manageable and compatible with conventional poly-Si TFT fabrication. As the ion dosages increase more than 5x10(15) cm(-2), however, the electrical characteristics of poly-Si TFTs were degraded due to the increase of trap state density caused by the fluorine segregation in the poly-Si film.
Fabrication of pattern-depended metal induced lateral crystallization polysilicon thin film transistors with NH3 plasma passivation effects
(2005)
Chou, Cheng-Wei
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Wu, Yung-Chun
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Wu, Yuan-Chun
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Chang, Ting-Chang
;
Liu, Po-Tsun
A pattern-dependent metal-induced lateral crystallized (PDMILC) poly-Si thin film transistor was successfully demonstrated and characterized. The fabrication of new PDMILC is simple with only four-mask process. After NH3 plasma passivation, the device performance was enhanced, including the high on/off current ration (>10(6)), the high mobilit (31.19 cm(2)/Vs), and the steep subtreshold swing (0.483 V/dec). The performance of PDMLC TFT with NH3 plasma passivation is superior to that of the counterpart without NH3 plasma passivation. The NH3 plasma treatment can result in the effective hydrogen passivation of the grain-boundary dangling bonds, and the nitrogen piile-up at SiO2/poly-Si interface.
Fabrication, characterization and simulation of Omega-gate twin poly-Si FinFET nonvolatile memory
(2013-07-22)
Yeh, Mu-Shih
;
Wu, Yung-Chun
;
Hung, Min-Feng
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Liu, Kuan-Cheng
;
Jhan, Yi-Ruei
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Omega-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Omega-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 10(4) program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.
High voltage characteristics of junctionless poly-silicon thin film transistors
(2013-09-16)
Cheng, Ya-Chi
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Wu, Yung-Chun
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Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
The breakdown voltage (V-BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V-BD of 53.4V is several times larger than V-BD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. (C) 2013 AIP Publishing LLC.
High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer
(2012-04-01)
Chen, Hung-Bin
;
Wu, Yung-Chun
;
Chen, Lun-Chun
;
Chiang, Ji-Hong
;
Yang, Chao-Kan
This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10(4) s at 150 degrees C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.
Improved performance of F-ions-implanted poly-Si thin-film transistors using solid phase crystallization and excimer laser crystallization
(2007-03-01)
Tu, Chun-Hao
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Yang, Che-Yu
;
Feng, Li-Wei
Polycrystalline silicon thin-film transistors (Poly-Si TFTs) with F-ions-implantation were investigated in this study. The electrical characteristics and reliability of the F-ions-implanted poly-Si TFTs were reported for solid phase crystallization (SPC) and excimer laser crystallization (ELC) methods respectively. The thermal annealing causes F-ions to pile up at the poly-Si interface, without the initial pad oxide deposition. With the introduction of fluorine in poly-Si film, the trap state density was effectively reduced. Also, the presence of strong Si-F bonds enhances electrical endurance against hot carrier impact by using F-ions-implantation. These improvements in electrical characteristics are even obvious for the ELC poly-Si TFTs compared to the SPC ones.