1. 目前位置：

瀏覽 的方式： 作者 Chen, Hung-Ming

跳到： 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
或是輸入前幾個字：  
顯示 21 到 40 筆資料，總共 152 筆 < 上一頁   下一頁 >
公開日期標題作者
2009Coupling- and ECP-Aware Metal Fill for Improving Layout Uniformity in Copper CMPCo, Yu-Lun; Chen, Hung-Ming; Cheng, Yi-Kan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2019Creation of 3D Textured Graphene/Si Schottky Junction Photocathode for Enhanced Photo-Electrochemical Efficiency and StabilityKu, Che-Kuei; Wu, Po-Hsieh; Chung, Cheng-Chu; Chen, Chun-Chi; Tsai, Kaijie; Chen, Hung-Ming; Chang, Yu-Cheng; Chuang, Cheng-Hao; Wei, Chuan-Yu; Wen, Cheng-Yen; Lin, Tzu-Yao; Chen, Hsuen-Li; Wang, Yen-Shang; Lee, Zhe-Yu; Chang, Un-Ru; Luo, Chih-Wei; Wang, Di-Yan; Hwang, Bing Joe; Chen, Chun-Wei; 電子物理學系; Department of Electrophysics
2006Design migration from peripheral ASIC design to area-10 flip-chip design by chip I/O planning and legalizationChang, Chia-Yi; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2008Design migration from peripheral ASIC design to area-I/O flip-chip design by chip I/O planning and legalizationChang, Chia-Yi; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2011Design Planning with 3D-Via Optimization in Alternative Stacking Integrated CircuitsLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Discrete dopant fluctuated 20nm/15nm-gate planar CMOSYang, Fu-Liang; Hwang, Jiunn-Ren; Chen, Hung-Ming; Shen, Jeng-Jung; Yu, Shao-Ming; Li, Yiming; Tang, Denny D.; 電信工程研究所; Institute of Communications Engineering
1-九月-2008Effective Decap Insertion in Area-Array SoC Floorplan DesignLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2008An effective decap insertion method considering power supply noise during floorplanningLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear ProgrammingLiu, Sean Shih-Ying; Lee, Chieh-Jui; Huang, Chuan-Chia; Chen, Hung-Ming; Lin, Chang-Tzu; Lee, Chia-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013Efficient Analog Layout Prototyping by Layout Reuse with Routing PreservationChin, Ching-Yu; Pan, Po-Cheng; Chen, Hung-Ming; Chen, Tung-Chieh; Lin, Jou-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2011Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2013Escaped Boundary Pins Routing for High-Speed BoardsChin, Ching-Yu; Kuan, Chung-Yi; Tsai, Tsung-Ying; Chen, Hung-Ming; Kajitani, Yoji; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Extending ML-OARSMT to Net Open Locator with Efficient and Effective Boolean OperationsJiang, Bing-Hui; Chen, Hung-Ming; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering
2011Fast Analog Layout Prototyping for Nanometer Design MigrationWeng, Yi-Peng; Chen, Hung-Ming; Chen, Tung-Chieh; Pan, Po-Cheng; Chen, Chien-Hung; Chen, Wei-Zen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesignLee, Ren-Jie; Lai, Ming-Fang; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2009Fast Flip-Chip Pin-Out Designation Respin for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2015A Fast Prototyping Framework for Analog Layout Migration With Planar PreservationPan, Po-Cheng; Chin, Ching-Yu; Chen, Hung-Ming; Chen, Tung-Chieh; Lee, Chin-Chieh; Lin, Jou-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2014Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green FunctionLiu, Sean Shih-Ying; Luo, Ren-Guo; Aroonsantidecha, Suradeth; Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green FunctionAroonsantidecha, Suradeth; Liu, Sean Shih-Ying; Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2018Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic BiochipsLu, Guan-Ruei; Kuo, Chun-Hao; Chiang, Kuen-Cheng; Banerjee, Ansuman; Bhattacharya, Bhargab B.; Ho, Tsung-Yi; Chen, Hung-Ming; 資訊工程學系; 電機學院; Department of Computer Science; College of Electrical and Computer Engineering
顯示 21 到 40 筆資料，總共 152 筆 < 上一頁   下一頁 >