National Chiao Tung University Institutional Repository：Browsing IR@NCTU

Browsing by Author CHEN, JE

Showing results 1 to 8 of 8

Issue Date	Title	Author(s)
1994	ALGEBRAIC DIVISION FOR MULTILEVEL LOGIC SYNTHESIS OF MULTIVALUED LOGIC-CIRCUITS	WANG, HM; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
7-Dec-1989	CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTS	CHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1994	COMPLETE TEST SET FOR MULTIPLE-VALUED LOGIC-NETWORKS	WANG, HM; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jul-1995	DISTRIBUTED FAULT SIMULATION FOR SEQUENTIAL-CIRCUITS BY PATTERN PARTITIONING	WU, WC; LEE, CL; CHEN, JE; LIN, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-1993	FAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITS	WANG, HM; LEE, CL; CHEN, JE; 交大名義發表; 電子物理學系; National Chiao Tung University; Department of Electrophysics
1-Sep-1995	IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS	LIANG, HC; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-1990	MY-BOX REPRESENTATION FOR FAULTY CMOS CIRCUITS	CHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-Dec-1991	SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITS	CHEN, JE; LEE, CL; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics

Showing results 1 to 8 of 8