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Showing results 1 to 8 of 8
Issue DateTitleAuthor(s)
Jul-2016Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication ConstraintsChen, Yi-Hang; Chen, Jian-Yu; Huang, Juinn-Dar; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-Jan-2014Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication ConstraintsChen, Yi-Hang; Chen, Jian-Yu; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2017Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor ArraysHuang, Juinn-Dar; Chen, Yi-Hang; Lu, Jia-Shin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional UnitsHuang, Juinn-Dar; Chen, Yi-Hang; Lin, Wan-Hsien; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015ROBDD-Based Area Minimization Synthesis for Reconfigurable Single-Electron Transistor ArraysChen, Yi-Hang; Chen, Yang; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Throughput Optimization for Latency-Insensitive System with Minimal Queue InsertionHuang, Juinn-Dar; Chen, Yi-Hang; Ho, Ya-Chien; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2014Two-Staged Parallel Layer-Aware Partitioning for 3D DesignsChen, Yi-Hang; Chen, Yi-Ting; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016應用於可重構式單電子電晶體陣列之合成技術陳詣航; 黃俊達; Chen, Yi-Hang; Huang, Juinn-Dar; 電子研究所
Showing results 1 to 8 of 8