Browsing by Subject 2-LEVEL
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| Issue Date | Title | Author(s) |
|---|---|---|
| 1-Jun-1993 | FAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITS | WANG, HM; LEE, CL; CHEN, JE; 交大名義發表; 電子物理學系; National Chiao Tung University; Department of Electrophysics |