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公開日期標題作者
1994ALGEBRAIC DIVISION FOR MULTILEVEL LOGIC SYNTHESIS OF MULTIVALUED LOGIC-CIRCUITSWANG, HM; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
7-十二月-1989CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTSCHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1994COMPLETE TEST SET FOR MULTIPLE-VALUED LOGIC-NETWORKSWANG, HM; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-1995DISTRIBUTED FAULT SIMULATION FOR SEQUENTIAL-CIRCUITS BY PATTERN PARTITIONINGWU, WC; LEE, CL; CHEN, JE; LIN, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-1993FAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITSWANG, HM; LEE, CL; CHEN, JE; 交大名義發表; 電子物理學系; National Chiao Tung University; Department of Electrophysics
1-九月-1995IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITSLIANG, HC; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-1990MY-BOX REPRESENTATION FOR FAULTY CMOS CIRCUITSCHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-十二月-1991SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITSCHEN, JE; LEE, CL; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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