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公開日期標題作者
1-一月-2017Asymmetry Hybrid Bonding Using Cu/Sn Bonding with Polyimide for 3D Heterogeneous Integration ApplicationsHuang, Yen-Jun; Chen, Hsiu-Chi; Yu, Ting-Yang; Lai, Bo-Hung; Shih, Yu-Chiao; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Development and Investigation of Ultra-Thin Buffer Layers Used in Symmetric Cu/Sn Bonding and Asymmetric Cu/Sn-Cu Bonding for Advanced 3D Integration ApplicationsChen, Hsiu-Chi; Kho, Yi-Tung; Huang, Yen-Jun; Hsieh, Yu-Sheng; Chang, Yao-Jen; Tang, Ya-Sheng; Yu, Ting-Yang; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016The Influence of Device Morphology on Wafer-Level Bonding with Polymer-Coated LayerLiang, Hao-Wen; Chen, Hsiu-Chi; Lin, Chien-Hung; Lee, Chia-Lin; Yang, Shan-Chun; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2018Investigation and Optimization of Ultrathin Buffer Layers Used in Cu/Sn Eutectic BondingTang, Ya-Sheng; Chen, Hsiu-Chi; Kho, Yi-Tung; Hsieh, Yu-Sheng; Chang, Yao-Jen; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2017三維積體電路之超薄緩衝層技術於銅/錫接合研究及開發陳秀齊; 陳冠能; Chen, Hsiu-Chi; Chen, Kuan-Neng; 電子研究所
顯示 1 到 5 筆資料，總共 5 筆