標題: The Influence of Device Morphology on Wafer-Level Bonding with Polymer-Coated Layer
作者: Liang, Hao-Wen
Chen, Hsiu-Chi
Lin, Chien-Hung
Lee, Chia-Lin
Yang, Shan-Chun
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Temporary bonding technology;3D integration;Device Morphology
公開日期: 1-一月-2016
摘要: Thetolerance of device morphology in wafer-level bonding through polymer-coated layer was investigated for the application of 3D integration. Several different pillar heights were fabricated on wafers to simulate the case of bonding with real devices on wafers. Overall, the wafer morphology with polymer-coated layer above devices less than 2 mu m can achieve excellent bonding quality. Furthermore, undamaged carrier wafers can be obtained after laser-assisted de-bonding technology, and post clean treatment. Based on bonding results, this research can provide a practical concept on device morphology for polymer-based temporary wafer-level bonding in 3D integration.
URI: http://hdl.handle.net/11536/147208
ISSN: 2164-0157
期刊: 2016 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC)
顯示於類別:會議論文