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公開日期標題作者
1-一月-1994CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGEKER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1995Complementary-LVTSCR ESD protection scheme for submicron CMOS IC'sKER, MD; WU, CY; CHANG, HH; CHENG, T; WU, TS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-1995COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICSKER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-1995MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATIONKER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-1995MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATIONKER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-1992A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSIWU, CY; KER, MD; LEE, CY; KO, J; 電控工程研究所; Institute of Electrical and Control Engineering
1994AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICSKER, MD; WU, CY; JIANG, HC; LEE, CY; KO, J; HSUE, P; 電控工程研究所; Institute of Electrical and Control Engineering
1-二月-1994TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERIONKER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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