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1-一月-2010Area-I/O RDL Routing for Chip-Package Codesign Considering Regional AssignmentLin, Kun-Sheng; Hsu, Hsin-Wu; Lee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2013Board- and Chip-Aware Package Wire PlanningLee, Ren-Jie; Hsu, Hsin-Wu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2011Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesignLee, Ren-Jie; Lai, Ming-Fang; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2009Fast Flip-Chip Pin-Out Designation Respin for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2011On Routing Fixed Escaped Boundary Pins for High Speed BoardsTsai, Tsung-Ying; Lee, Ren-Jie; Chin, Ching-Yu; Kuan, Chung-Yi; Chen, Hung-Ming; Kajitani, Yoji; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
21-四月-2011Pin-out Designation Method for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming
2011Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design FlowLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2013A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design FlowLee, Ren-Jie; Chen, Hung-Ming; 交大名義發表; National Chiao Tung University
2009晶片—封裝—印刷電路板共同設計之演算法李仁傑; Lee, Ren-Jie; 陳宏明; Chen, Hung-Ming; 電子研究所
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