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公開日期標題作者
1997An area and time efficient adder for multiple additions with different word-lengthLiang, BS; Nieh, YC; Jen, CW; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-五月-2002Base model transmission for 3D graphics in a network environmentLiang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2000Computation-effective 3-D graphics rendering architecture for embedded multimedia systemLiang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2000Computation-effective 3-D graphics rendering architecture for embedded multimedia systemLiang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997Enacting a software development processChen, MF; Liang, BS; Lin, RJR; Wang, FJ; 交大名義發表; 資訊工程學系; National Chiao Tung University; Department of Computer Science
1995A hardware-efficient architecture for 3-D graphics processorLiang, BS; Nieh, YC; Niou, YP; Jen, CW; Chuang, G; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-九月-2002Index rendering: Hardware-efficient architecture for 3-D graphics in multimedia systemLiang, BS; Lee, YC; Yeh, WC; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2000A project model for software developmentLiang, BS; Chen, JN; Wang, FJ; 資訊科學與工程研究所; Institute of Computer Science and Engineering
25-十月-2001Speed up of rendering pipeline by deferred lighting and triple queue structureLiang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics