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公開日期標題作者
2-十一月-2015Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-offCheng, Ya-Chi; Chen, Hung-Bin; Chang, Chun-Yen; Wu, Yi-Kang; Shih, Yi-Jia; Shao, Chi-Shen; Wu, Yung-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICsCheng, Ya-Chi; Chen, Hung-Bin; Chang, Chun-Yen; Cheng, Chun-Hu; Shih, Yi-Jia; Wu, Yung-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion EffectLin, Ming-Huei; Shih, Yi-Jia; Liu, Chien; Chiu, Yu-Chien; Fan, Chia-Chi; Liou, Guan-Lin; Cheng, Chun-Hu; Chang, Chun-Yen; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
5-十二月-2018Improved Thermal Stability and Stress Immunity in Highly Scalable Junctionless FETs Using Enhanced-Depletion ChannelsLiu, Chien; Cheng, Chun-Hu; Lin, Ming-Huei; Shih, Yi-Jia; Hung, Yu-Wen; Fan, Chia-Chi; Chen, Hsuan-Han; Chen, Wan-Hsin; Hsu, Chih-Chieh; Shih, Bing-Yang; Chiu, Yu-Chien; Chou, Wu-Ching; Hsu, Hsiao-Hsuan; Chang, Chun-Yen; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
2016具有多層P/N 3D結構通道 之高度微縮60奈米短通道無接面場效電晶體施宜嘉; 張俊彥; Shih, Yi-Jia; Chang, Chun-Yen; 電子研究所
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