標題: | A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs |
作者: | Cheng, Ya-Chi Chen, Hung-Bin Chang, Chun-Yen Cheng, Chun-Hu Shih, Yi-Jia Wu, Yung-Chun 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2016 |
摘要: | This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I-on/I-off current ratio (> 10(9)), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications. |
URI: | http://hdl.handle.net/11536/134333 |
ISBN: | 978-1-5090-0638-0 |
期刊: | 2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY |
顯示於類別: | 會議論文 |