標題: | High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETs |
作者: | Kuo, Po-Yi Lu, Yi-Hsien Chao, Tien-Sheng 電子物理學系 Department of Electrophysics |
關鍵字: | Gate-all-around (GAA);junctionless (JL);sidewall-damascened nanowires (SWDNWs) |
公開日期: | 1-十一月-2014 |
摘要: | The gate-all-around sidewall-damascened sub-10- nm in situ n(+)-doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm(2) cross-sectional area have been successfully fabricated and demonstrated in the category of poly-Si NWs JL transistors for the first time. Some key properties are explored: 1) novel SWDNW processes; 2) dependence of threshold voltage (V-TH) and subthreshold swing (S.S.) on dimension of in situ n(+)-doped poly-Si NWs in GAA SWDNW-JLFETs; and 3) thermal stability of main electrical characteristics under high operating temperature. The high-performance GAA SWDNW-JLFETs show good electrical characteristics: 1) steep S.S. similar to 75 mV/decade; 2) low gate supply voltage (V-G) = 1.5 V; 3) high ON/OFF currents ratio (I-ON/I-OFF) similar to 8 x 10(7) and significantly highthermal stability without implantation processes and hydrogenrelated plasma treatments for future 3-D integrated circuits, system-on-panel, and system-on-chip applications. |
URI: | http://dx.doi.org/10.1109/TED.2014.2354436 http://hdl.handle.net/11536/123944 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2014.2354436 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 61 |
Issue: | 11 |
起始頁: | 3821 |
結束頁: | 3826 |
顯示於類別: | 期刊論文 |