標題: | Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique |
作者: | Su, Chun-Jung Tsai, Tzu-I Lin, Horng-Chih Huang, Tiao-Yuan Chao, Tien-Sheng 電子物理學系 電子工程學系及電子研究所 奈米中心 Department of Electrophysics Department of Electronics Engineering and Institute of Electronics Nano Facility Center |
關鍵字: | Accumulation mode;Gate-all-around;Junctionless;Low-temperature poly-Si;Nanowire |
公開日期: | 1-一月-1970 |
摘要: | "In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al2O3 gate stack using an implant-free approach. Since the source/drain and channel regions are sharing one in situ phosphorous-doped poly-Si material, the process flow and cost could be efficiently reduced. Owing to the GAA configuration and small volume of NW channels, the fabricated devices with heavily doped channels display superior switching behaviors and excellent immunity to short-channel effects. Besides, the negative fixed charges in Al2O3 are found to be helpful to obtain desirable positive threshold voltages for the n(+)-poly-Si channel devices. Thus, the simple and low-cost fabrication method along with excellent device characteristics makes the proposed GAA NW transistor a promising candidate for future 3-D electronics and system-on-panel applications." |
URI: | http://dx.doi.org/339 http://hdl.handle.net/11536/16762 |
ISSN: | 1931-7573 |
DOI: | 339 |
期刊: | NANOSCALE RESEARCH LETTERS |
Volume: | 7 |
Issue: | |
結束頁: | 1 |
顯示於類別: | 期刊論文 |