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公開日期標題作者
2012An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM ArrayLin, Geng-Cing; Wang, Shao-Cheng; Lin, Yi-Wei; Tsai, Ming-Chien; Chuang, Ching-Te; Jou, Shyh-Jye; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Asymmetrical Write-Assist for Single-Ended SRAM OperationLin, Jihi-Yu; Tu, Ming-Hsien; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAMWang, Shao-Cheng; Lin, Geng-Cing; Lin, Yi-Wei; Tsai, Ming-Chien; Chiu, Yi-Wei; Jou, Shyh-Jye; Chuang, Ching-Te; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2012A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing TracingTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Lu, Chien-Yu; Lin, Yuh-Jiun; Wang, Meng-Hsueh; Huang, Huan-Shun; Lee, Kuen-Di; Shih, Wei-Chiang (Willis); Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2010Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-AssistTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010奈米級CMOS靜態隨機存取記憶體之負/正偏壓溫度效應劣化現象與雜訊邊界量測電路蔡銘謙; Tsai, Ming-Chien; 周世傑; Jou, Shyh-Jye; 電子研究所
顯示 1 到 6 筆資料，總共 6 筆