Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Abstract

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V(DD), an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 mu W.