次臨界操作及低功率內嵌式靜態隨機存取記憶體設計與實現

Abstract

在電路設計中要節省功率消耗，降低電源電壓是一個很有效的方法。電路可以藉由在次臨界電壓下操作達到超低功耗的效能。然而，電路在次臨界電壓下操作會到遇到明顯下降的Ion/Ioff比例和嚴重的製程、電壓和溫度變異。特別是在次臨界電壓下設計堅固和可靠以栓鎖器為基礎架構的SRAM記憶胞將為更加的困難。在這篇論文中，介紹了SRAM的背景知識和可靠性的問題。並提出SRAM在低電壓設計的挑戰。之後，提出兩種SRAM記憶胞和輔助電路來實現低電壓和次臨界電壓操作的性能。

首先，提出一個資料感知電源切斷寫入輔助之12T位元交錯次臨界電壓操作的SRAM記憶胞，以減輕在深次100奈米製程低電壓下伴隨著嚴重的元件變異提高資料寫入的能力。這個無干擾的特性可以方便地使用在位元交錯的架構中，可在減少一個字元中發生多個位元錯誤的次數，並採用錯誤檢查糾正的技術增強軟性錯誤的免疫力。提出的12T SRAM單元使用40奈米互補式金屬氧化物半導體技術實現一個4096位元的SRAM區塊。測試晶片可以從典型的操作電壓至350毫伏進行操作（約比臨界電壓低100毫伏），最低之操作電壓受限於讀取操作。資料可以在操作電壓低至300毫伏仍被成功地寫入。測量的最大操作頻率為11.5百萬赫茲與22微瓦操作在350毫伏，室溫攝式25度。

此論文再提出一個改善寫入能力以降低寫入最低電壓之數據感知電源切斷寫入輔助12T SRAM記憶胞。此外，提出一種自我適應的資料感知維持器，以減輕維持器在維持器電流、讀取電流及位元線漏電流之間的衝突，使維持器的設計更加簡易並提高讀取的穩定性和改進單端讀取的最低操作電壓。以40奈米的製程技術製造一個8192位元的測試晶片，每條位元線上有64個記憶胞，可分別在6百萬赫茲、250毫伏及4百萬赫茲、230毫伏下操作。每條位線上有256、512和1024個記憶胞之測試區塊驗證自我適應的資料感知維持器降低9%至17%的最低讀取電壓值。

To save power in integrated circuit designs, reducing supply voltage is an effective method. Circuits can achieve ultra-low-power dissipation by operating in subthreshold region. However, circuits encounter obviously degraded Ion/Ioff ratio and severe process, voltage, temperature (PVT) variations in subthreshold region. Particularly, it is more difficult to design robust and reliable SRAM cells in subthreshold region due to latch-based architectures. In this dissertation, background knowledge and reliability issues of SRAMs are introduced. Low-voltage design challenges of SRAMs are presented. Then, two SRAM cells and the assistant circuits are proposed to achieve low-voltage and subthreshold operation.

First, a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100nm processes is proposed. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm General Purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV (~100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 uW at 350 mV, 25 degree C.

This thesis further proposes a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN) is illustrated. Moreover, we propose an adaptive data-aware keeper (DAK) to mitigate the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line achieves VMIN of 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 17% at low supply voltages.