標題: | Design and Iso-Area V-min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS |
作者: | Chang, Ming-Hung Chiu, Yi-Te Hwang, Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Bit-interleaving scheme;iso-area analysis;subthreshold static random-access memory (SRAM) |
公開日期: | 1-七月-2012 |
摘要: | "In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-mu W active power consumption." |
URI: | http://hdl.handle.net/11536/16754 |
ISSN: | 1549-7747 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 59 |
Issue: | 7 |
結束頁: | 429 |
顯示於類別: | 期刊論文 |