次微米內嵌式記憶體之低功耗設計

Abstract

對於便攜式和可穿戴設備，能量效率是延長電池壽命的一個重要問題。在現代積體電路，越來越多的晶載記憶體被整合在一個晶片上。可以預見的是，靜態隨機存取記憶體不僅將主導晶片的面積而且也將主導晶片的功耗和性能。因此，低電壓操作與低功耗的靜態隨機存取記憶體需求急劇增加。在本論文中，首先對靜態隨機存取記憶體的背景知識和記憶體單元的穩定性進行介紹。然後，對操作在低電壓時靜態隨機存取記憶體的可靠性問題進行了討論。

接著，動態電壓調整是一種降低功率消耗常用的技術。在這篇論文中，我們提出了一個脈衝控制動態電壓調整的方法，透過降低未被選取記憶庫的供電電壓以減少功耗。我們所提出的記憶體模組能夠操作在低電壓區間。透過運用一個已驗證過之單端無擾動9T次臨界操作記憶體單元結合資料察覺寫入字元線架構，使得記憶體模組能在較低的操作電壓下操作，以降低動態功率消耗。我們使用 65 奈米低漏電 CMOS 製程製作一個包含 8 千位元記憶體模組的測試晶片來驗證結果。量測結果顯示，在 500 kHz 的操作頻率下， 脈衝控制動態電壓調整的方法可減少記憶體陣列的功率消耗高達64%。此時被選取記憶庫的供電電壓為 0.5 V，而未被選取記憶庫的供電電壓為 0.35 V。

最後，對兩個低功率消耗的傳統6T記憶體模組進行說明。傳統上，基於對速度和面積（密度）的考量，設計者通常會使用傳統的 6T 記憶體單元，並盡可能的把更多記憶體單元放在同一條位元線上，以節省面積。使用階層式位元線架構將資料從本地位元線傳輸到全局位元線是記憶體模組中常用的方法。在這篇論文中，我們以 28 奈米高性能移動應用 CMOS 製程模擬兩種不同類型的階層式位元線架構做比較。模擬結果顯示傳輸閘階層式位元線架構配合電荷分配讀取技術相較於反及閘階層式位元線架構可以減少 59% 的位元線功率消耗。 接著對從記憶體編譯器產生的低功耗的記憶體模組修改做介紹。對模組的修改有兩點，一個是降低在每個位元線上的記憶體單元數量，另一種則是採用電流電流鎖存感測放大器，取代電壓感測讀出放大器。佈局後的模擬結果顯示出可以減少近20%的動態功率消耗。

For portable and wearable devices, energy efficiency is an important issue to last the life time of batteries. In modern ICs, more and more on-chip memories are being integrated on a die. It is well known that Static Random Access Memory (SRAM) will dominate not only area but also power, and performance. Therefore,the demand of low voltage and low power SRAM circuit designs with operation frequency of several MHz have increased dramatically. In the thesis, the background knowledge and the definitions of cell stability for SRAM are introduced are first presented. Then the reliability issue of low supply voltage for SRAM is discussed.

Second, dynamic voltage scaling is a common technique to save power consumption. In this thesis, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to reduce power consumption by lowering unselected sub-bank's supply voltage. The proposed SRAM macro is capable of operating in low-voltage regime. In the SRAM macro, we utilize our previous silicon-proved 9T SRAM bitcell[1] which used data-aware Write word-line structure to lower the dynamic power by operating at a lower operation voltage. An 8 kbits SRAM macro is fabricated in 65nm LP CMOS technology. Measurement results shows that the proposed PC-DVS scheme reduces the array power up to 64% at 500kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.

Finally, the two low power design of conventional 6T SRAM macro are described. Traditionally, for speed and area (density) consideration, designers would prefer to use the conventional 6T SRAM bitcell and place more bitcells on a bitline to save area. Using Hierarchical Bit-line structures to transmit the data from local bit-lines to global bit-lines is a common method in SRAM macro. In this thesis, two types of Hierarchical Bit-line schemes is compared in 28nm HPM technology. Simulation results show that the pass-gate Hier-BL with the charge sharing Read scheme can reduce at least 59% power as compare to NAND-gate based Hier-BL. Then the modifications on a low power SRAM macro generated by memory compiler are introduced. Two modifications are applied to the macro, one is to reduce the number of bitcells on each bit-line, and the other one is using current-latched sense amplifiers instead of voltage-latched sense amplifiers. The post-layout simulation results shows the reduction of dynamic power is near 20% at all three corners.