超低功耗次臨界操作靜態隨機存取記憶體的設計與實現

Abstract

近來，超低功耗電池操作元件的需求持續增加。當在低電壓操作時若效能可以符合系統需求則降低操作電壓便可以大幅降低功耗。更進一步，系統如果操作在次臨界區，便可以達到超低功耗的需求。然而，當系統操作在次臨界區時，便會面臨Ion/Ioff比率降低、嚴重的製程電壓溫度(PVT)變異等等挑戰，此對於佔晶片系統中大部分之內嵌式靜態記憶體(SRAM)設計更是極大之挑戰。本論文中，將提出三個SRAM單元與他們的輔助電路，以達次臨界區操作的目的。 此論文先提出一個以單端8T SRAM單元的256x16位元次臨界操作SRAM設計，此設計加入非對稱寫入並輔以虛接地偏壓架構與正回授感應維持電路。此非對稱寫入並輔以虛接地偏壓架構改善寫入邊界達35%操作電壓與提升寫入效能。隔絕的讀取緩衝電路與正回授感應維持電路相結合可提升讀取雜訊邊界達50%操作電壓，並藉著不需位元線預充操作而使位元達到全擺幅，並使位元線感應電路的功耗達到最小。使用90nm CMOS佈局後模擬結果顯示在600mV操作電壓下，可達到234MHz操作頻率。測試晶片量測結果也證明此電路在200mV操作電壓下可達到6MHz操作頻率，並且其功耗僅需10.4μW。模擬與量測結果證明了，這個記憶體設計可以達到設計目標在0.6V操作電壓下，6MHz操作頻率。更進一步，這個記憶體設計可以在次臨界區穩健地操作以達到超低電壓功耗的需求。 第二個設計為一個單端無擾動9T次臨界操作SRAM單元結合十字點資料察覺寫入字元線架構。為了達到穩健的次臨界區操作，此9T單元消除了讀取擾動與寫入半選擇擾動。此電路採用一個可調式讀取操作時間追溯電路與負電壓字元線電路，以分別達成PVT變動容忍的讀取操作與增強寫入能力。此SRAM以65nm低漏電CMOS製程設計一個72Kb SRAM模組的測試晶片。量測結果顯示在1.2V到0.35V(約深入臨界電壓0.15V)可達到完全正確的全操作。在次臨界區下，以0.35V操作此72Kb SRAM可操作於229KHz與4.05µW功耗。資料維持最低可達0.275V並僅以2.29µW待命功耗。在0.5V操作電壓每次操作最低能量為4.5pJ，當操作電壓由1.2V降到0.5V可省下8.07倍的操作能量。 最後，此論文介紹一個絕對寫入無擾動12T次臨界SRAM單元並結合十字點資料察覺寫入字元線與寫入回授打斷架構。為了穩健的次臨界區操作，此12T單元不只消除了讀取擾動更消除了寫入擾動。更進一步，此12T單元以十字點資料覺察寫入字元線與寫入回授打斷架構來達成不需寫入輔助電路的絕對寫入操作。此12T單元在65nm低漏電高臨界電壓製程設計，並與相等面積的6T與10T單元做比較。模擬結果證明，這個12T單元在製程變異下，可操作範圍可以由1.2V下降到0.3V(大約低於臨界電壓0.35V)操作電壓。與相同面積的6T單元相比較，在每條BL有相同數量的單元下，此12T單元擁有較高的讀取與寫入操作穩定度與較高的讀取正確性。與相同面積的10T單元比較，此12T單元擁有較高的寫入能力。

Recently, the demand for ultra-low power dissipation battery-operated devices is increasing. When the performance at low supply voltage (VDD) meets system requirement, scaling down the supply voltage reduces power dissipation significantly. A circuit can achieve ultra-low power dissipation by operating in subthreshold region, but the circuit will encounter significantly degraded Ion/Ioff ratio and the large process, voltage, temperature (PVT) variations in subthreshold region. Moreover, it is a great challenge to design embedded SRAM, which occupies the large portion of SOC. In the thesis, the background knowledge and low-voltage design challenges of SRAM are first presented. The reliability issue of low supply voltage for SRAM is discussed, and the definitions of cell stability for SRAM are introduced. Then, three SRAM cells and their assistant circuits are introduced to achieve low-voltage and subthreshold operation. First, a 256*16 bits subthreshold SRAM, based on a single-ended 8T cell with asymmetrical Write-assistant virtual ground biasing scheme and positive feedback sensing keeper, is described. The asymmetrical Write-assistant virtual ground biasing scheme improves the Write Margin (35% of supply voltage) and enhances the Write performance. The isolated Read buffer with positive feedback sensing keeper enhances the Read Static Noise Margin (RSNM) to 50% of the supply voltage, enables the elimination of bit line (BL) precharge operation and full-rail BL swing to minimize the power dissipation of BL sensing circuit. The post-layout simulation results show that the chip implemented by 90nm standard performance process achieves 234MHz operation frequency at 600mV supply voltage. The measured results verify that the chip can achieve 6MHz operation frequency at 200mV VDD with power consumption of 10.4μW. The simulated and measured results prove that the SRAM design achieve the design target of 6MHz operation frequency at 0.6V VDD. Moreover, the SRAM design has robust functionality in subthreshold region to achieve the requirement of the ultra-low power dissipation. Second, a single-ended disturbance-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure is illustrated. The 9T cell eliminates not only Read disturbance but also Write Half-Select disturbance for robust subthreshold operation. An adaptive Read operation timing tracing circuit and negative bit-line circuit are employed in the design for PVT variation-tolerant Read operation and Write-ability enhancement, respectively. A test chip with 72Kb SRAM macros is implemented in 65nm low-leakage CMOS technology. The measured results demonstrate error free full functionality from 1.2V down to 0.35V (~0.15V lower than the threshold voltage). In subthreshold region, the 72Kb SRAM operates at 229KHz with 4.05µW power consumption. Data is held down to 0.275V with 2.29µW Standby power. The minimum energy per operation is 4.5pJ at 0.5V, and 8.07X energy saving is achieved by scaling VDD from 1.2V to 0.5V. Finally, an absolutely Write disturbance-free 12T subthreshold SRAM cell with cross-point data-aware Write word-line and Write feedback-cutoff structure is illustrated. The 12T cell eliminates not only Read disturbance but also Write half-selected disturbance for robust subthreshold operation. Furthermore, the 12T SRAM cell with cross-point data-aware Write word-line and Write feedback-cutoff structure achieves absolute Write operation without any Write-assistant circuit. The 12T SRAM cell is designed in 65nm low-leakage HVT CMOS technology to compare with iso-area 6T and 10T SRAM cells. The simulation results prove that the 12T SRAM cell is functional from 1.2V VDD to 0.3V VDD (~0.35V lower than threshold voltage) with process variation. Compared to the iso-area 6T SRAM cell, the 12T SRAM has high stability at Read and Write operation and has more Read correctness with the same number of cells per BL. Compared to the iso-area 10T SRAM cell, the 12T SRAM has higher Write-ability.