低功率8T靜態隨機存取記憶體和次臨界多埠暫存器的設計與實現

Abstract

嵌入式記憶體在現今高效能低功率晶片佔了重要的地位。傳統的6T靜態隨機存取記憶體在先進製程的技術下面臨了許多的挑戰。在此篇論文中，將會討論NBTI/PBTI效應對於靜態隨機存取記憶體的影響，並且提出了一個能夠降低此效應影響的架構和方法，而降低輻度高達32%-48%。另一個去解決傳統6T靜態隨機存取記憶體問題的方法是設計一個新的儲存架構。這篇論文呈現了一個新的8T架構，相較於傳統的設計，這個設計的資料的穩定性有1.74倍提升。此外，這篇論文提出一個新的介面電路能夠讓8T相容於傳統6T靜態隨機存取記憶體周邊電路。

另一項重要的靜態隨機存取記憶體的應用是多埠暫存器設計。在傳統的設計上，為了達到多埠的功能，設計者去會去增加儲存單元的埠數目。然而，在先進製程下，這個設計也將面臨許多的問題。因此一個可以應用在超長指令集架構的數位訊號處理器中並且操作在1伏到0.25伏的多埠暫存器設計在此篇論文呈現，其設計的架構是以多組區塊來達成多埠的實現。為了能讓暫存器操作在次臨界電壓，像是雙Vt的儲存單元設計，負電壓寫入機制，改進的讀取機制等，使之可以操作在低電壓下。這個可以支援同時4讀4寫的暫存器系以UMC 90nm CMOS製程設計，操作電壓在0.25伏特時，22.3-22.9微瓦功率消耗。

Embedded memory plays a significant role in high performance and low power VLSI technology. Stability and area of traditional 6T SRAM is difficult to scale down in future process due to the serious PVT variation and other effect, such as reliability issue: NBTI and PBTI. In this thesis, detailed analysis of timing control degradation caused by NBTI and PBTI on SRAM is presented. Furthermore, NBTI/PBTI tolerant design for nanoscale CMOS SRAM is also presented, which reduces 32%-48% degradation. Another method to address drawbacks of 6T SRAM cell is to design another new bit-cell, presented in this thesis. This new bit-cell eliminates read disturb and half-select disturb of 6T bit-cell and has 1.75X read SNM improvement when compared to the conventional 6T SRAM cell. An interface circuit design lets the unique structure of new 8T bit-cell combine the peripheral circuit of 6T SRAM without declining performance.

Another important SRAM design is multi-port SRAM-based register file. Similarly, multi-port bit-cell in nano-scale process or ultra low voltage works fail. As a result, a micro-watt multi-port register file with wide operating voltage range for micro-power applications is presented. Multibank architecture for simultaneous access with collision detecting technique is proposed. The architecture can be applied to VLIW DSP, and has been analyzed under wide operating voltage range between 1V to 0.25V with varies process corner. Negative voltage write scheme ensures successful write in deep sub-threshold region. Also, an improved read buffer footer and controllable pre-charge in read scheme are designed. A 4W/4R 16KB register file is implemented in UMC 90nm CMOS technology. The simulation results show that the maximum active power of multi-port register file can achieve near 22.3-22.9uW at 485 KHz under 0.25V.