標題: 應用於生醫感測平台之 28 奈米極低功率近/次臨界 先進先出記憶體設計
28nm Ultra-Low Power Near-/Sub-threshold First-In- First-Out (FIFO) Memory for Bio-Sensing Platforms
作者: 徐維伸
莊景德
黃威
Hsu, Wei-Shen
Chuang, Ching-Te
Hwang, Wei
電子研究所
關鍵字: 低功率;自我控制;先進先出記憶體;low power;self-timed;FIFO memory
公開日期: 2016
摘要: 在許多系統晶片應用上,先進先出記憶體很常被用作資料暫存和流程控制。 對於生醫感測平台而言,生醫感測器必須極為輕巧,不管是穿戴或植入在人體上。 同時,延長的電池壽命是必須的。因此,極低功率消耗的先進先出記憶體變成一 個重要的設計議題。在本論文中,首先提出一個新的位元交錯架構,它可以有效 減少位元線上的電容及功率消耗,以及可以節省一條長金屬導線讓整體的運作速 度不會卡在指標上。第二,提出一用在位元交錯架構的 10T 近/次臨界隨機存取 記憶體儲存單元,它有 2.4 倍的讀取靜態雜訊邊界和減少位元線上資料依賴所造 成的漏電流。第三,自我時序控制的指標可以減少一條常金屬導線及時鐘訊號, 這比起之前的暫存器指標減少 59%的功率消耗。第四,適應性時間控制電路可以 隨著製程、電壓、溫度變異追蹤最差情形的讀寫情況。第五,列層級功率切換控 制電路可以適當的調整所需要的電壓輸出,它可以減少約 60.5%的整體功率消耗。 最後,以聯電 28 奈米高介電質金屬閘極技術來實作一個 8kb 10T 隨機存取記憶 體為基礎及運用上述節能技術的極低功率先進先出記憶體。比起之前的先進先出 記憶體,它減少了 47 倍的功率消耗及減省了 2.7 倍的面積,是特別適合用在生 醫感測平台的先進先出記憶體。
FIFO memory is commonly used for data buffers and flow control in many SoC applications. For bio-sensing platforms, the biomedical sensors must be lightweight with small form factor, either wearable or implanted into human body. Simultaneously, extended battery lifetime is needed. Therefore, an ultra-low power FIFO memory becomes a significant design concern. In this thesis, a novel bit- interleaving scheme is proposed firstly to reduce the bit-line capacitance efficiently and the power consumption, and saves a long wire routing and the operation speed won’t be dominated by the pointers. Secondly, a 10T near-/sub-threshold SRAM bit-cell for bit-interleaving scheme is proposed, which has 2.4X write SNM improvement and reduces data-dependent bit-line leakage. Thirdly, self-timed pointers are proposed to save a long metal line and a clock signal, which further save the power consumption about 59% comparing to shift-register-based pointers. Fourthly, adaptive timing control circuitries are presented to track the worst case read/write situation under the serious PVT variations. Fifthly, a power switch control circuitry with bank-column-control is proposed to switch the supply voltage to an adequate value, which can save the power consumption about 60.5%. Finally, an 8kb 0.6V/0.43V ultra-low power FIFO memory in UMC 28nm HKMG technology with the proposed 10T SRAM bit-cell and all energy-efficient technics is implemented. It has 47X power improvement and 2.7X area improvement comparing to previous FIFO memories, which is specifically suitable for bio- sensing platforms.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070250205
http://hdl.handle.net/11536/139449
顯示於類別:畢業論文