應用於生醫感測及物聯網平台之28奈米極低功率近/次臨界多使用者先進先出記憶體設計

Abstract

在許多系統晶片應用上，先進先出記憶體很常被用作資料暫存和流程控制。同時，延長的電池壽命是必須的。因此，極低功率消耗的先進先出記憶體變成一個重要的設計議題。另外，為了降低記憶體在晶片中的面積，相較於傳統每個使用者對應各自先進先出記憶體，在本論文中提出了多使用者先進先出記憶體及優化過的記憶體位置分配來減少功率消耗。第二，提出一用雙端無擾動12T近/次臨界隨機存取記憶體儲存單元結合十自點資料察覺寫入字元線架構。為了到穩健的低壓操作，此12T單元消除了讀取擾動與寫入半選擇擾動。此電路同時採用一個可調式讀取操作時間追溯電路與負電壓字元線電路，以達到PVT變動容忍的讀取操作及增強寫入能力。第三，提出了漣波字元線架構利用漣波緩衝器將字元線分割成數個區塊降低導線延遲。第四，為了減少記憶體位置分配之鏈接表面積，本論文架構中以連續十六筆資料輸入輸出為一單位，因此控制訊號的傳遞也是很重要的議題，這邊提出自我時序控制的指標比起之前的移位暫存器減少59%的功率消耗。第四，鏈接表以硬體描述語言做驗證。最後，以聯電28奈米高介電質金屬閘極技術來實作一個4kb 12T雙端隨機存取記憶體為基礎及運用上述節能技術的極低功率先進先出記憶體。比起之前的先進先出記憶體，它能同時進行兩個寫入或者兩個讀取的執行，在相同級更好的的靜態訊邊界下提高了兩倍傳輸量，是適合用在生醫感測及物聯網平台的先進先出記憶體。

IFO memory is commonly used for data buffers and flow control in many SoC applications. Simultaneously, extended battery lifetime is needed. Therefore, an ultra-low power FIFO memory becomes a significant design concern. Besides, to reduce memory area in chip, compared to conventional design that each user has its own FIFO memory, in this thesis, a novel multi-user FIFO memory and optimized memory allocation algorithm are proposed to reduce power consumption. Secondly, a two port disturbance-free 12T near-/sub-threshold SRAM bit-cell with cross-point data-aware Write word-line structure is illustrated. The 12T cell eliminates not only read disturbance but also write half-select disturbance for robust sub-threshold operation. An adaptive read operation timing tracing circuit and negative bit-line circuit are employed in the design for PVT variation-tolerant read operation and write ability enhancement. Thirdly, the proposed ripple bit-line structure divide the bit-line into several segments. Therefore, the wire delay can be reduced apparently. Fourthly, to reduce area overhead of the link table used for memory address allocation, in this thesis, we set continuous sixteen pieces of data as an unit. Therefore, the self-timed pointers are proposed to save a long metal line and a clock signal, which further save the power consumption about 59% comparing to shift-register-based pointers. Fifthly, the link table is verified by Verilog. Finally, a 4kb ultra-low power FIFO memory in UMC 28nm HKMG technology with the proposed 12T two port SRAM bit-cell is implemented. It can execute two write or two read operation simultaneously. Under the condition with the same or better SNM comparing to previous FIFO memories, this design has double throughput which is suitable for bio-sensing and IoT platforms.